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參數(shù)資料
| 型號： | LMX2377USLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PQCC24 |
| 封裝： | PLASTIC, CSP-24 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 3181K |
| 代理商： | LMX2377USLBX |
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1.0 Functional Description
(Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (ID
Main Bit = 0) in the steady state mode, to
3.8 mA (ID
Main Bit = 1) in Fastlock. When the F
LD output
is configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 F
o
LD
for details on how to configure the F
o
LD
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the F
LD is programmed to
Reset Aux PLL Counters
, both
the Aux feedback divider and the Aux reference divider are
held at their load point. When the
Reset Main PLL
Counters
is programmed, both the Main feedback divider
and the Main reference divider are held at their load point.
When the
ResetAll Counters
mode is enabled, all feedback
dividers and reference dividers are held at their load point.
When the device is programmed to normal operation, both
the feedback divider and reference divider are enabled and
resume counting in ‘close’ alignment to each other. Refer to
Section 2.8 F
o
LD
for more details.
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R divders can be monitored
by selecting the appropriate F
LD word. This is essential
when performing OSC
in
or f
sensitivity measurements. Re-
fer to the
Test Setups
section for more details. Refer to
Section 2.8 F
LD
for details on how to route the appropriate
divder output to the F
o
LD pin.
1.9 POWER CONTROL
Each synthesizer in the LMX2377U device is individually
power controlled by device powerdown bits. The powerdown
word is comprised of the
PWDN Main
(
PWDN Aux
) bit, in
conjuction with the
TRI-STATE ID
Main
(
TRI-STATE ID
o
Aux
) bit. The powerdown control word is used to set the
operating mode of the device. Refer to
Sections 2.4.4,
2.5.4, 2.6.4
, and
2.7.4
for details on how to program the Main
or Aux powerdown bits.
When either the Main synthesizer or the Aux synthesizer
enters the powerdown mode, the respective prescaler,
phase detector, and charge pump circuit are disabled. The
D
Main (D
Aux), f
Main (f
Aux), and f
Main pins are all
forced to a high impedance state. The reference divider and
feedback divider circuits are held at the load point during
powerdown. The oscillator buffer is disabled when both the
Main and Aux synthesizers are powered down. The OSC
in
pin is forced to a HIGH state through an approximate 100 k
resistance when this condition exists. When either synthe-
sizer is activated, the respective prescaler, phase detector,
charge pump circuit, and the oscillator buffer are all powered
up. The feedback divider, and the reference divider are held
at load point. This allows the reference oscillator, feedback
divider, reference divider and prescaler circuitry to reach
proper bias levels. After a finite delay, the feedback and
reference dividers are enabled and they resume counting in
‘close’ alignment (the maximum error is one prescaler cycle).
The MICROWIRE control register remains active and ca-
pable of loading and latching data while in the powerdown
mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
TRI-STATE ID
o
0
1
0
1
PWDN
0
0
1
1
Operating Mode
PLL Active, Normal Operation
PLL Active, Charge Pump Output in High Impedance State
Synchronous Powerdown
Asynchronous Powerdown
Notes:
1. TRI-STATE ID
o
refers to either the TRI-STATE ID
o
Main or TRI-STATE ID
o
Aux bit .
2. PWDN refers to either the PWDN Main or PWDN Aux bit.
L
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