參數(shù)資料
型號(hào)： LMX2377U
廠(chǎng)商： National Semiconductor Corporation
英文描述： PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
中文描述： PLLatinum⑩超低功耗雙頻率合成射頻個(gè)人通信
文件頁(yè)數(shù)： 32/44頁(yè)
文件大?。?/td> 3181K
代理商： LMX2377U
1.0 Functional Description
(Continued)
1.5 PHASE/FREQUENCY DETECTORS
The Main and Aux phase/frequency detectors are driven
from their respective N and R counter outputs. The maxi-
mum frequency for both the Main and Aux phase detector
inputs is 10 MHz. The phase/frequency detector outputs
control the respective charge pumps. The polarity of the
pump-up or pump-down control signals are programmed
using the
PD_POL Main
or
PD_POL Aux
control bits, de-
pending on whether the Main orAux VCO characteristics are
positive or negative. Refer to
Sections 2.4.2
and
2.6.2
for
more details. The phase/frequency detectors have a detec-
tion range of 2
π
to +2
π
. The phase/frequency detectors
also receive a feedback signal from the charge pump in
order to eliminate dead zone.
PHASE COMPARATOR AND INTERNAL CHARGE PUMP CHARACTERISTICS
20022611
Notes:
1.
2.
3.
4.
5.
The minimum width of the pump-up and pump-down current pulses occur at the D
o
Main or D
o
Aux pins when the loop is phase locked.
The diagram assumes positive VCO characteristics, i.e. PD_POL Main or PD_POL Aux = 1.
F
r
is the phase detector input from the reference divider (R counter).
F
p
is the phase detector input from the programmable feedback divder (N counter).
D
o
refers to either the Main or Aux charge pump output.
1.6 CHARGE PUMPS
The charge pump directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of the
VCO. The charge pump steers the VCO control voltage
towards V
P
Main or V
P
Aux during pump-up events and
towards GND during pump-down events. When locked, D
o
Main or D
o
Aux are primarily in a TRI-STATE mode with
small corrections occuring at the phase comparator rate. The
charge pump output current magnitude can be selected by
toggling the
ID
o
Main
or
ID
o
Aux
control bits.
1.7 MICROWIRE SERIAL INTERFACE
The programmable register set is accessed via the MI-
CROWIRE serial interface. The supply for the MICROWIRE
circuitry is separate from the rest of the IC to allow direct
connection to 1.8V devices. The interface is comprised of
three signal pins: Clock, Data and LE (Latch Enable). Serial
data is clocked into the 22-bit shift register on the rising edge
of Clock. The last two bits decode the internal control regis-
ter address. When LE transitions HIGH, data stored in the
shift register is loaded into one of four control registers
depending on the state of the address bits. The MSB of Data
is loaded in first. The synthesizers can be programmed even
in power down mode. A complete programming description
is provided in
Section 2.0 Programming Description
.
1.8 MULTI-FUNCTION OUTPUTS
The LMX2377U device’s F
LD output pin is a multi-function
output that can be configured as the Main synthesizer Fast-
Lock output, an open drain analog lock detect output,
counter reset, or used to monitor the output of the various
reference divider (R counter) or feedback divider (N counter)
circuits. The F
o
LD control word is used to select the desired
output function. When the PLL is in powerdown mode, the
F
o
LD output is pulled to a LOW state. A complete program-
ming description of the multi-function output is provided in
Section 2.8 F
o
LD
.
1.8.1 Open Drain Analog Lock Detect Output
An analog lock detect status generated from the phase
detector is available on the F
LD output pin if selected. The
lock detect output goes to a high impedance state when the
charge pump is inactive. It goes low when the charge pump
is active during a comparison cycle. When viewed with an
oscilloscope, and when a pull-up resistor is used, narrow
negative pulses are observed when the charge pump turns
on. The lock detect output signal is an open drain configu-
ration.
Three separate lock detect signals are routed to the multi-
plexer. Two of these monitor the ‘lock’ status of the individual
synthesizers. The third detects the condition when both the
Main and Aux synthesizers are in a ‘locked state’. External
circuitry however, is required to provide a steady DC signal
to indicate when the PLL is in a locked state. Refer to
Section 2.8 F
o
LD
for details on how to program the different
lock detect options.
L
www.national.com
32
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參數(shù)描述
LMX2377U WAF 制造商:Texas Instruments 功能描述:
LMX2377USLBX 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2377USLEX 功能描述:IC FREQ SYNTH DUAL 20LAMUCSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2377UTM 功能描述:IC FREQ SYNTH DUAL 20TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2377UTMX 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
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