- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358887 > LMX2377U (National Semiconductor Corporation) PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications PDF資料下載
參數(shù)資料
| 型號： | LMX2377U |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinum⑩超低功耗雙頻率合成射頻個人通信 |
| 文件頁數(shù)： | 31/44頁 |
| 文件大?。?/td> | 3181K |
| 代理商： | LMX2377U |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當(dāng)前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2377U, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, programmable reference R and
feedback N frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via
the reference divider to obtain a comparison reference fre-
quency. This reference signal, F
r
, is then presented to the
input of a phase/frequency detector and compared with the
feedback signal, F
p
, which was obtained by dividing the VCO
frequency down by way of the feedback divider. The
phase/frequency detector measures the phase error be-
tween the F
and F
signals and outputs control signals that
are directly proportional to the phase error. The charge pump
then pumps charge into or out of the loop filter based on the
magnitude and direction of the phase error. The loop filter
converts the charge into a stable control voltage for the
VCO. The phase/frequency detector’s function is to adjust
the voltage presented to the VCO until the feedback signal’s
frequency and phase match that of the reference signal.
When this “Phase-Locked” condition exists, the VCO fre-
quency will be N times that of the comparison frequency,
where N is the feedback divider ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for both the Main and Aux
PLLs is provided from an external reference via the OSC
in
pin. The reference buffer circuit supports input frequencies
from 2 to 40 MHz with a minimum input sensitivity of 0.5 V
.
The reference buffer circuit has an approximate V
CC
/2 input
threshold and can be driven from an external CMOS or TTL
logic gate. Typically, the OSC
in
pin is connected to the output
of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R COUNTERS)
The reference dividers divide the reference input signal,
OSC
in
, by a factor of R. The output of the reference divider
circuits feeds the reference input of the phase detector. This
reference input to the phase detector is often referred to as
the comparison frequency. The divide ratio should be chosen
such that the maximum phase comparison frequency (F
φ
Main
or F
φ
Aux
) of 10 MHz is not exceeded.
The Main and Aux reference dividers are each comprised of
15-bit CMOS binary counters that support a continuous in-
teger divide ratio from 2 to 32767. The Main and Aux refer-
ence divider circuits are clocked by the output of the refer-
ence buffer circuit which is common to both.
1.3 PRESCALERS
The f
Main and f
Main input pins drive the input of a
bipolar, differential-pair amplifier. The output of the bipolar,
differential-pair amplifier drives a chain of ECL D-type
flip-flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent feedback dividers.
The Main PLL complementary inputs can be driven differen-
tially, or the negative input can be AC coupled to ground
through an external capacitor for single ended configuration.
A 16/17 or a 32/33 prescale ratio can be selected for the
LMX2377U Main synthesizer. On the other hand, the Aux
PLL is only intended for single ended operation. An 8/9 or a
16/17 prescale ratio can be selected for the LMX2377U Aux
synthesizer.
1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N
COUNTERS)
The programmable feedback dividers operate in concert with
the prescalers to divide the input signal f
by a factor of N.
The output of the programmable reference divider is pro-
vided to the feedback input of the phase detector circuit. The
divide ratio should be chosen such that the maximum phase
comparison frequency (F
φ
Main
or F
φ
Aux
) of 10 MHz is not
exceeded.
The programmable feedback divider circuit is comprised of
an A counter (swallow counter) and a B counter (program-
mble binary counter). The Main N_CNTRA and the Aux
N_CNTRA counters are both 5-bit CMOS swallow counters,
programmable from 0 to 31. The Main N_CNTRB and Aux
N_CNTRB counters are both 13-bit CMOS binary counters,
programmable from 3 to 8191. A continuous integer divide
ratio is achieved if N
≥
P
*
(P1), where P is the value of the
prescaler selected. Divide ratios less than the minimum con-
tinuous divide ratio are achievable as long as the binary
programmable counter value is greater than the swallow
counter value (N_CNTRB
≥
N_CNTRA). Refer to
Sections
2.5.1, 2.5.2, 2.7.1
and
2.7.2
for details on how to program
the N_CNTRA and N_CNTRB counters. The following equa-
tions are useful in determining and programming a particular
value of N:
N = (P x N_CNTRB) + N_CNTRA
f
IN
= N x F
φ
Definitions:
F
φ
:
Main or Aux phase detector comparison
frequency
f
IN
:
Main or Aux input frequency
N_CNTRA: Main or Aux A counter value
N_CNTRB: Main or Aux B counter value
P:
Preset
modulus
prescaler
Main synthesizer: P = 16 or 32
Aux synthesizer: P = 8 or 16
of
the
dual
moduIus
L
www.national.com
31
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2471 | 3.6 GHz Delta-Sigma Fractional-N PLL with 1.7 GHz Integer-N PLL |
| LMX2502LQ1635 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2502LQX1635 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2502 | PLLatinum⑩ Frequency Synthesizer System with Integrated VCO |
| LMX2505LQ1321 | PLLatinu Dual Frequency Synthesizer System with Integrated VCOs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2377U WAF | 制造商:Texas Instruments 功能描述: |
| LMX2377USLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2377USLEX | 功能描述:IC FREQ SYNTH DUAL 20LAMUCSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2377UTM | 功能描述:IC FREQ SYNTH DUAL 20TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2377UTMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。