參數(shù)資料
型號(hào)： LMX2371
廠商： National Semiconductor Corporation
英文描述： PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器)
中文描述： PLLatinum雙頻率合成射頻個(gè)人通信（PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器）
文件頁(yè)數(shù)： 12/24頁(yè)
文件大?。?/td> 516K
代理商： LMX2371
1.0 Functional Description
(Continued)
1.8.1 Lock Detect Output
An analog lock detect status generated from the phase detector is available on the Fo/LD output pin, if selected. The lock detect
output goes high when the charge pump is inactive. It goes low when the charge pump is active during a comparison cycle. The
lock detect signal output is an open drain configuration. When a PLL is in power down mode, the respective lock detect output
is always high.
1.8.2 FastLock Outputs
When configured as FastLock mode, the current can be increased 4x while maintaining loop stability by synchronously switching
a parallel loop filter resistor to ground, resulting in a
～
2x change in loop bandwidth. The zero gain crossover point of the open loop
gain, or the loop bandwidth is effectively shifted up in frequency by a factor of
√
4 = 2 during FastLock mode. For
ω
’ = 2
ω
, the
phase margin during FastLock will also remain constant. The charge pump current is programmed via MICROWIRE interface.
When the charge pump circuit receives an input to deliver 4 times the normal current per unit phase error, an open drain NMOS
on chip device (FoLD) switches in a second resistor element to ground. The user calculates the loop filter component values for
the normal steady state considerations. The device configuration ensures that as long as a second resistor equal to the primary
resistor value is wired in appropriately, the loop will lock faster without any additional stability considerations to account for.
1.9 POWER CONTROL
Each PLL is individually power controlled by device power-down (
PWDN
) bits. The
Main_PWDN
and
Aux_PWDN
bits determine
the state of power control. Activation of any PLL power-down condition results in the disabling of the respective N-counter and
de-biasing of its respective f
IN
input (to a high impedance state). The R-counter functionality also becomes disabled under this
condition.
The reference oscillator input block is powered down when both Main_PWDN and Aux_PWDN bits are asserted. The OSC
in
pin
reverts to a high impedance state when this condition exists. Power down forces the respective charge pump and phase com-
parator logic to a TRI-STATE condition. During the power down condition, both N- and R-counters are held at reset. Upon pow-
ering up, the N-counter resumes counting in “close” alignment with the R-counter. The maximum error is at most one prescaler
cycle. The MICROWIRE interface remains active and it is capable of loading and latching in data during all of the power down
modes.
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The LMX237x register set can be accessed through the MICROWIRE interface. A 22-bit shift register is used as a temporary reg-
ister to indirectly program the on-chip registers. The shift register consists of a 20-bit DATA[19:0] field and a 2-bit ADDRESS[1:0]
field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift register in
the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data stored
in the shift register is loaded into the addressed latch.
MSB
LSB
DATA[19:0]
ADDRESS[1:0]
21
2
1
0
2.1.1 Registers’ Address Map
When Load Enable (LE) is transitioned high, data is transferred from the 22-bit shift register into the appropriate latch depending
on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the corre-
sponding internal register.
ADDRESS[1:0]
FIELD
0
0
1
1
REGISTER
ADDRESSED
Aux_R Register
Aux_N Register
Main_R Register
Main_N Register
0
1
0
1
L
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參數(shù)描述
LMX2371 WAF 制造商:Texas Instruments 功能描述:
LMX2371SLBX 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TM 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TMX 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2372 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
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