參數(shù)資料
型號(hào)： LMX2371
廠商： National Semiconductor Corporation
英文描述： PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器)
中文描述： PLLatinum雙頻率合成射頻個(gè)人通信（PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器）
文件頁(yè)數(shù)： 11/24頁(yè)
文件大?。?/td> 516K
代理商： LMX2371
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer
such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The fre-
quency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feed-
back [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to
obtain a comparison reference frequency. This reference signal (f
R
) is then presented to the input of a phase/frequency detector
and compared with the feedback signal (f
), which is obtained by dividing the VCO frequency down by way of the N-counter. The
phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control
voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback
signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency
will be N times that of the comparison frequency, where N is the integer divide ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSC
pin.
OSC
can operate up to 50 MHz with input sensitivity of 0.5 V
. The OSC
pin drives both the Main R-counter and the Auxiliary
R-counter. The input has a V
/2 input threshold that can be driven from an external CMOS or TTLlogic gate. Typically, the OSC
in
is connected to the output of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R-COUNTERS)
The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.
Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.
1.3 PRESCALERS
The complimentary f
and f
inputs drive a differential-pair amplifier which feeds to the respective prescaler. The Main PLL
complementary f
1 and f
1b inputs can be driven differentially, or the negative input can be AC coupled to ground through an
external capacitor for single ended configuration. The Auxiliary PLL has the complimentary input AC coupled to ground through
an internal 10 pF capacitor. The Auxilllary PLL complimentary input is not brought out to a pin, and is intended for single ended
configuration only. The LMX237x has a dual modulus prescaler with 2 selectable modulo. For PLL’s rated at 2.5 GHz or 2.0 GHz
a 32/33 or 16/17 prescaler is available. For PLL’s rated at 1.2 GHz a 16/17 or 8/9 can be chosen. Both Main and Auxiliary pres-
calers’ outputs drive the subsequent CMOS flip-flop chain comprising the programmable N feedback counters. The proper pres-
caler value must be chosen to in order not to exceed the maximum CMOS frequency. For f
IN
>
1.2 GHz, the 32/33 prescaler must
be selected, similarly for f
IN
>
550 MHz, the prescaler value must be at least 16/17, and for f
IN
<
550 MHz, an 8/9 prescaler value
is allowable.
1.4 FEEDBACK DIVIDERS (N-COUNTERS)
The Main andAuxiliary N-counters are clocked by the output of Main andAux prescalers respectively. The N-counter is composed
of a 13-bit integer divider and a 5-bit swallow counter. Selecting a 32/33 prescaler provides a minimum continuous divider range
from 992 to 262,143 while selecting a 16/17 or 8/9 prescaler value allows for continuous divider values between and 240 to
131,087 and 56 to 65,559 respectively.
1.5 PHASE/FREQUENCY DETECTORS
The phase/frequency detectors are driven from their respective N- and R-counter outputs. The maximum frequency at the phase
detector inputs is 10 MHz unless limited by the minimum continuous divide ratio of the dual-modulus prescaler. The phase de-
tector output controls the charge pump. The polarity of the pump-up or pump-down control is programmed using
Main_PD_POL
or
Aux_PD_POL
, depending on whether Main or Auxiliary VCO characteristics is positive or negative. The phase detector also
receives a feedback signal from the charge pump in order to eliminate dead zone.
1.6 CHARGE PUMPS
The phase detector’s current source output pumps charge into an external loop filter, which then integrates into the VCO’s control
voltage. The charge pump steers the charge pump output CP
to V
(pump-up) or Ground (pump-down). When locked, CP
is
primarily in a TRI-STATE mode with small corrections. The charge pump output current magnitude can be selected as 1.0 mA or
4.0 mA by programming the
Main_ICP
o
_4X
or
Aux_ICP
o
_4X
bits.
1.7 MICROWIRE SERIAL INTERFACE
The programmable register set is accessed through the Microwire serial interface. The interface is comprised of three signal pins:
clock, data and load enable (LE). The supply for the MICROWIRE circuitry is separate from the rest of the IC to allow for controller
voltages down to 1.8V. Serial data is clocked into the 22-bit shift register upon the rising edge of clock. The MSB bit of data shifts
first. The last two bits decode the internal register address. On the rising edge of LE, data stored in the shift register is loaded into
one of the four latches according to the address bits. The synthesizer can be programmed even in power down state. A complete
programming description is followed in Section 2.0.
1.8 MULTIFUNCTION OUTPUTS
The LMX2370/LMX2371/LMX2372 FoLD output pin can be configured as the FastLock output or CMOS programmed output,
analog lock detects as well as showing the internal block status such as the counter outputs.
L
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2371 WAF 制造商:Texas Instruments 功能描述:
LMX2371SLBX 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TM 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TMX 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2372 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
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