參數(shù)資料
型號(hào)： LMX2370TM/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 4/25頁(yè)
文件大?。?/td> 577K
代理商： LMX2370TM/NOPB
1.0 Functional Description (Continued)
rent is programmed via MICROWIRE interface. When the
charge pump circuit receives an input to deliver 4 times the
normal current per unit phase error, an open drain NMOS on
chip device (FoLD) switches in a second resistor element to
ground. The user calculates the loop filter component values
for the normal steady state considerations. The device con-
figuration ensures that as long as a second resistor equal to
the primary resistor value is wired in appropriately, the loop
will lock faster without any additional stability considerations
to account for.
1.9 POWER CONTROL
Each PLL is individually power controlled by device power-
down (PWDN) bits. The Main_PWDN and Aux_PWDN bits
determine the state of power control. Activation of any PLL
power-down condition results in the disabling of the respec-
tive N-counter and de-biasing of its respective f
IN input (to a
high impedance state). The R-counter functionality also be-
comes disabled under this condition.
The reference oscillator input block is powered down when
both Main_PWDN and Aux_PWDN bits are asserted. The
OSC
in pin reverts to a high impedance state when this
condition exists. Power down forces the respective charge
pump and phase comparator logic to a TRI-STATE condition.
During the power down condition, both N- and R-counters
are held at reset. Upon powering up, the N-counter resumes
counting in “close” alignment with the R-counter. The maxi-
mum error is at most one prescaler cycle. The MICROWIRE
interface remains active and it is capable of loading and
latching in data during all of the power down modes.
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The LMX237x register set can be accessed through the MICROWIRE interface. A 22-bit shift register is used as a temporary
register to indirectly program the on-chip registers. The shift register consists of a 20-bit DATA[19:0] field and a 2-bit AD-
DRESS[1:0] field as shown below. The address field is used to decode the internal register address. Data is clocked into the shift
register in the direction from MSB to LSB, when the CLOCK signal goes high. On the rising edge of Load Enable (LE) signal, data
stored in the shift register is loaded into the addressed latch.
MSB
LSB
DATA[19:0]
ADDRESS[1:0]
21
2 1
0
2.1.1 Registers’ Address Map
When Load Enable (LE) is transitioned high, data is transferred from the 22-bit shift register into the appropriate latch depending
on the state of the ADDRESS[1:0] bits. A multiplexing circuit decodes these address bits and writes the data field to the
corresponding internal register.
ADDRESS[1:0]
REGISTER
FIELD
ADDRESSED
0
Aux_R Register
0
1
Aux_N Register
1
0
Main_R Register
1
Main_N Register
LMX2370
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