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參數(shù)資料
| 型號： | LMX2370TM/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封裝： | PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 15/25頁 |
| 文件大小： | 577K |
| 代理商： | LMX2370TM/NOPB |
Application Information (Continued)
other terms in the gain and phase Equations (5), (6) will have
to compensate by the corresponding “1/w” or “1/w
2” factor.
Examination of Equations (3), (4), (6) indicates the damping
resistor variable R2 could be chosen to compensate the “w”
terms for the phase margin. This implies that another resistor
of equal value to R2 will need to be switched in parallel with
R2 during the initial lock period. We must also ensure that
the magnitude of the open loop gain, H(s)G(s) is equal to
zero at wp’ = 2wp. K
VCO,K
φ, N, or the net product of these
terms can be changed by a factor of 4, to counteract the w
2
term present in the denominator of Equations (3), (4). The K
φ
term was chosen to complete the transformation because it
can readily be switch between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
FASTLOCK CIRCUIT IMPLEMENTATION
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX233xA PLL is shown in Figure 5.
When a new frequency is loaded, and the RF Icp
o bit is set
high the charge pump circuit receives an input to deliver 4
times the normal current per unit phase error while an open
drain NMOS on chip device switches in a second R2 resistor
element to ground. The user calculates the loop filter com-
ponent values for the normal steady state considerations.
The device configuration ensures that as long as a second
identical damping resistor is wired in appropriately, the loop
will lock faster without any additional stability considerations
to account for. Once locked on the correct frequency, the
user can return the PLL to standard low noise operation by
sending a MICROWIRE instruction with the RF Icp
o bit set
low. This transition does not affect the charge on the loop
filter capacitors and is enacted synchronous with the charge
pump output. This creates a nearly seamless change be-
tween Fastlock and standard mode.
10102643
FIGURE 4. Open Loop Response Bode Plot
10102644
FIGURE 5. Fastlock PLL Architecture
LMX2370
www.national.com
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| LMX2370TMX/NOPB | 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 45MHz to 2500MHz 20-Pin TSSOP T/R |
| LMX2371 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| LMX2371 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2371SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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