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參數(shù)資料
| 型號： | LMX2370 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個人通訊的雙通道頻率合成器) |
| 中文描述： | PLLatinum雙頻率合成射頻個人通信（PLLatinum技術(shù)用于射頻個人通訊的雙通道頻率合成器） |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 516K |
| 代理商： | LMX2370 |
2.0 Programming Description
(Continued)
2.3.5 PLL Prescaler Select (P_Aux, P_Main)
The LMX2370, LMX2371 and LMX2372 contain two dual modulus prescalers. A 32/33 or a 16/17 prescaler can be selected for
the 2.5 GHz and 2.0 GHz RF synthesizers in the LMX2370 and LMX2371 respectively. The 16/17 prescaler is only rated for input
frequencies below 1.2 GHz. A 16/17 or an 8/9 prescaler can be selected for the both 1.2 GHz synthesizers on the LMX2372 as
well as the 1.2 GHz synthesizers on the LMX2370 and LMX2371. The 8/9 prescaler is only rated for input frequencies below
550 MHz.
Prescaler Value
P_Main, (Main_N18) or
P_Aux (Aux_N18)
0
1
2.5 GHz PLL
2.0 GHz PLL
1.2 GHz PLL
16/17
32/33
16/17
32/33
8/9
16/17
Allowable Prescaler Values
2.0 GHz PLL
32/33
16/17 or 32/33
16/17 or 32/33
PLL Input Frequency
f
IN
>
1.2 GHz
550
<
f
IN
<
1200 MHz
f
IN
<
550 MHz
2.5 GHz PLL
32/33
16/17 or 32/33
16/17 or 32/33
1.2 GHz PLL
NA
16/17
8/9 or 16/17
2.3.5.1 Pulse Swallow Function
f
VCO
= [(P x B) + A] x f
OSC
/R
f
VCO
:
Output frequency of external voltage controlled oscillator (VCO)
B:
Preset divide ratio of binary 13-bit programmable counter (3 to 8191)
A:
Preset divide ratio of binary 5-bit swallow counter
0
≤
A
≤
31 {P=32}
0
≤
A
≤
15 {P=16}
0
≤
A
≤
7 {P=8}
A
≤
B
f
OSC
:
Output frequency of the external reference frequency oscillator
R:
Preset divide ratio of binary 15-bit programmable reference counter (3 to 32767)
P:
Preset modulus of dual modulus prescaler (P = 8, 16, or 32)
2.3.6 PLL Power Down Control (Aux_PWDN, Main_PWDN)
The
Aux_PWDN (Aux_N19)
and
Main_PWDN (Main_N19
) bits are used to power down either the Main orAuxiliary PLL’s charge
pump portion, or the entire PLL block depending on the setting of the respective charge pump TRI-STATE bit (Aux_CP
o
_TRI or
Main_CP
o
_TRI) in the R_CNTR register. The power-down mechanism is described below. The R and N counters for each respec-
tive PLL are disabled and held at reset during the synchronous and asynchronous power down modes. This will allow a smooth
acquisition of the Main RF signal when the oscillator input buffer is still active (Auxiliary loop powered up) and vice versa. Upon
powering up, both R and N counters will start at the “zero” state, and the relationship between R and N will not be random.
Synchronous Power Down Mode
One of the PLL loops can be synchronously powered down by first setting the respective loop’s TRI-STATE mode bit LOW (R17
= 0) and then asserting its power down mode bit (N19 = 1). The power down function is gated by the charge pump. Once the
power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and TRI-STATE bits Aux_CP
_TRI (Aux_R17)
or Main_CP
o
_TRI (Main_R17) are loaded, the part will go into power down mode upon the completion of a charge pump pulse
event.
Asynchronous Power Down Mode
One of the PLL loops can be asynchronously powered down by first setting the respective loop’s TRI-STATE mode bit HI (R17
= 1) and then asserting its power down mode bit (N19 = 1). The power down function is NOT gated by the charge pump. Once
the power down program bits Aux_PWDN (Aux_N19) and Main_PWDN (Main_N19) and its respective TRI-STATE bit Aux_CP
o-
_TRI (Aux_R17) or Main_CP
o
_TRI (Main_R17) are loaded, the part will go into power down mode immediately.
L
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