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參數(shù)資料
| 型號： | LMX2370 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器) |
| 中文描述： | PLLatinum雙頻率合成射頻個(gè)人通信（PLLatinum技術(shù)用于射頻個(gè)人通訊的雙通道頻率合成器） |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 516K |
| 代理商： | LMX2370 |
2.0 Programming Description
(Continued)
2.2 PROGRAMMABLE REFERENCE DIVIDERS (Main and Aux R Counters)
2.2.1 Aux_R Register
If the ADDRESS[1:0] field is set to 0 0, data is transferred from the 22-bit shift register into the Aux_R register when Load Enable
(LE) signal goes high. TheAux_R register sets theAux PLL’s 15-bit R-counter divide ratio and various programmable modes. The
divide ratio is put into the Aux_R_CNTR[14:0] field. The divider ratio must be
≥
2. For the description of bits Aux_R15–Aux_R19
see Section 2.4.
Most Significant Bit
21
20
SHIFT REGISTER BIT LOCATION
13
12
11
Data Field
Least Significant Bit
2
1
Address Field
19
18
17
16
15
14
10
9
8
7
6
5
4
3
0
Aux_R
F
F
A
o
_
A
o
_
A
Aux_R_CNTR[14:0]
0
0
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
2.2.2 Main_R Register
If the ADDRESS[1:0] field is set to 1 0, data is transferred from the 22-bit shift register into the Main_R register which sets the
Main PLL’s 15-bit R-counter divide ratio when Load Enable (LE) signal goes high. The divide ratio is put into the
Main_R_CNTR[14:0] field. The divider ratio must be
≥
2. For the description of bits Main_R15–Main_R19 see Section 2.4.
Most Significant Bit
21
20
SHIFT REGISTER BIT LOCATION
13
12
11
Data Field
Least Significant Bit
2
1
Address Field
19
18
17
16
15
14
10
9
8
7
6
5
4
3
0
Main_R
F
F
M
o
_
M
o
_
M
Main_R_CNTR[14:0]
1
0
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
2.2.3 Reference Divide Ratio (Main and Auxiliary R-Counters)
If theADDRESS[1:0] field is set to 0 0 or 1 0 (00 forAux and 10 for Main) data is transferred MSB first from the 22-bit shift register
into a latch which sets the respective 15-bit R-counter. Serial data format is shown below.
Main_R_CNTR[14:0] or Aux_R_CNTR[14:0]
R10
R9
R8
R7
0
0
0
0
0
0
1
1
1
Divide Ratio
2
3
32,767
R14
0
0
1
R13
0
0
1
R12
0
0
1
R11
0
0
1
R6
0
0
1
R5
0
0
1
R4
0
0
1
R3
0
0
1
R2
0
0
1
R1
1
1
1
R0
0
1
1
0
0
1
Note:
R-counter divide ratio must be from 2 to 32,767.
2.3 PROGRAMMABLE FEEDBACK [N] DIVIDERS
2.3.1 Aux_N Register
If the ADDRESS[1:0] field is set to 0 1, data is transferred from the 22-bit shift register into the Aux_N register which sets the Aux-
iliary PLL’s 18-bit N-counter, prescaler value and power-down bit. The 18-bit N-counter consists of a 5-bit swallow
counter, Aux_A_CNTR[4:0], and a 13-bit programmable counter, Aux_B_CNTR[12:0]. Serial data format is shown below.
L
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