參數(shù)資料
型號(hào)： LMX2355SLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, QCC24
封裝： PLASTIC, CSP-24
文件頁(yè)數(shù)： 17/23頁(yè)
文件大小： 403K
代理商： LMX2355SLBX
Pin Descriptions
Pin No. for
TSSOP
Package
Pin No. for
CSP
Package
Pin
Name
I/O
Description
1
24
OUT0
O
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
21
V
CCRF
—
RF PLL power supply voltage input. Must be equal to Vcc
IF. May range from
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
32
V
PRF
—
Power supply for RF charge pump. Must be
≥ V
CCRF and VCCIF.
43
CP
oRF
O
RF charge pump output. Connected to a loop filter for driving the control input
of an external VCO.
5
4
GND
—
Ground for RF PLL digital circuitry.
6
5
fin RF
I
RF prescaler input. Small signal input from the VCO.
7
6
fin RF
I
RF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
8
7
GND
—
Ground for RF PLL analog circuitry.
9
8
OSC
RF
I
Dual mode oscillator output or RF R counter input. Has a V
CC/2 input threshold
when configured as an input and can be driven from an external CMOS or TTL
logic gate.
10
9
OSC
IF
I
Oscillator input which can be configured to drive both the IF and RF R counter
inputs or only the IF R counter depending on the state of the OSC
programming bit. (See functional description 1.1 and programming description
3.1.)
11
10
Fo/LD
O
Multiplexed output of N or R divider and RF/IF lock detect. CMOS output. (See
programming description 3.1.5.)
12
11
RF_EN
I
RF PLL Enable. Powers down RF N and R counters, prescaler, and
TRI-STATE charge pump output when LOW. Bringing RF_EN high powers up
RF PLL depending on the state of RF_CTL_WORD. (See functional description
1.9.)
13
12
IF_EN
I
IF PLL Enable. Powers down IF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW. Bringing IF_EN high powers up IF PLL
depending on the state of IF_CTL_WORD. (See functional description 1.9.)
14
13
CLOCK
I
High impedance CMOS Clock input. Data for the various counters is clocked
into the 24-bit shift register on the rising edge.
15
14
DATA
I
Binary serial data input. Data entered MSB first. The last two bits are the
control bits. High impedance CMOS input.
16
15
LE
I
Load Enable high impedance CMOS input. Data stored in the shift registers is
loaded into one of the 4 internal latches when LE goes HIGH. (See functional
description 1.7.)
17
16
GND
—
Ground for IF analog circuitry.
18
17
fin IF
I
IF prescaler complimentary input. A bypass capacitor should be placed as
close as possible to this pin and be connected directly to the ground plane.
19
18
fin IF
I
IF prescaler input. Small signal input from the VCO.
20
19
GND
—
Ground for IF digital circuitry.
21
20
CPo
IF
O
IF charge pump output. For connection to a loop filter for driving the input of an
external VCO.
22
21
V
PIF
—
Power supply for IF charge pump. Must be
≥ V
CCRF and VCCIF.
23
22
V
CCIF
—
IF power supply voltage input. Must be equal to V
CCRF. Input may range from
2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this
pin and be connected directly to the ground plane.
24
23
OUT1
O
Programmable CMOS output. Level of the output is controlled by IF_N [18] bit.
LMX2354
www.national.com
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