參數(shù)資料
型號(hào)： LMX2354TM/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24
封裝： TSSOP-24
文件頁(yè)數(shù)： 4/26頁(yè)
文件大?。?/td> 453K
代理商： LMX2354TM/NOPB
Functional Description (Continued)
1.8 Fo/LD MULTIFUNCTION OUTPUT
The Fo/LD output pin can deliver several internal functions
including analog/digital lock detects, and counter outputs.
See programming description 4.1.5 for more details.
1.8.1 Lock Detect
A digital filtered lock detect function is included with each
phase detector through an internal digital filter to produce a
logic level output available on the Fo/LD output pin if se-
lected. The lock detect output is high when the error between
the phase detector inputs is less than 15 ns for 5 consecutive
comparison cycles. The lock detect output is low when the
error between the phase detector outputs is more than 30 ns
for one comparison cycle. An analog lock detect signal is
also selectable. The lock detect output is always low when
the PLL is in power down mode. See programming descrip-
tions 4.1.5, 5.6–5.8 for more details.
1.9 POWER CONTROL
Each PLL is individually power controlled by device enable
pins or MICROWIRE power down bits. The enable pins
override the power down bits
except for the V2_EN bit. The
RF_EN pin controls the RF PLL; IF_EN pin controls the IF
PLL. When both pins are high, the power down bits deter-
mine the state of power control (see programming descrip-
tion 5.2.1.2). Activation of any PLL power down mode results
in the disabling of the respective N counter and de-biasing of
its respective fin input (to a high impedance state). The R
counter functionality also becomes disabled when the power
down bit is activated. The reference oscillator block powers
down and the OSC
IF pin reverts to a high impedance state
when both RF and IF enable pins or power down bit’s are
asserted,
unless the V2_EN bit (RF_R[22]) is high. Power
down forces the respective charge pump and phase com-
parator logic to a TRI-STATE condition. A power down
counter reset function resets both N and R counters. Upon
powering up the N counter resumes counting in “close”
alignment with the R counter (The maximum error is one
prescaler cycle). The MICROWIRE control register remains
active and capable of loading and latching in data during all
of the power down modes.
2.0 Major Differences between the LMX2354 and the LMX2350/52
LMX2350/52
LMX2354
OSC
IF
Supports resonator mode.
Does not support resonator mode.
Low modulus prescale (Note 7)
5-bit A counter, so if 16/17 prescale, bit-5 is
the unused place holder.
4-bit A/B counters, so if 8/9/12/13, bit-4 is
the unused place holder.
RF Prescaler
LMX2350 — 32/33 or 16/17
LMX2354 — 16/17/20/21 or 8/9/12/13
LMX2352 — 16/17 or 8/9
Fractional Engine
Standard. Fractional Compensation cannot
be turned off.
Similar structure to the LMX2350/52, but with
some modifications for improved phase noise
and spurs. Fractional Compensation can be
turned off.
Note 7: If the LMX2354 is replacing a LMX2350/52 in a design, and you are using the lower modulus prescale value (16/17 on the LMX2350 changes to 8/9/12/13
on the LMX2354), the unused prescaler bit of the LMX2350/52 needs to shift down one bit from N<9> to N<8>.
LMX2354
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PDF描述
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