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參數(shù)資料
| 型號： | LMX2354TM/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2354TM/NOPB |
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Functional Description (Continued)
LMX2354 RF N Counter Register in Fractional Mode with P = 8/9/12/13
C Word
B Word
A Word
Fractional Word
N
19
18
17
16
15
14
13
12
11
10
987
6
5432
1
1–23
Divide ratios less than 24 are impossible since it is required that C
≥3
These bits are used for
the fractional word when
the part is operated in
fractional mode
24–39
Some of these values are legal divide ratios, some are not
40*
000000
0
1
0100
0
41
000000
0
1
0100
0
1
...
272
000001
0
1000
0
...
......
.
....
.
16,383
111111
1
1101
1
*Minimum continuous divide ratio is P
[MAX{A,B}+2]
1.3.1 Prescaler
The RF and IF inputs to the prescaler consist of fin and /fin;
which are complimentary inputs to differential pair amplifiers.
The complimentary inputs are internally coupled to ground
with a 10 pF capacitor. These inputs are typically AC coupled
to ground through external capacitors as well. The input
buffer drives the A counter’s ECL D-type flip flops in a dual
modulus configuration. An 8/9/12/13 or 16/17/20/21 prescale
ratio can be selected for the LMX2354. The IF circuitry for
both the LMX2354 contains an 8/9 prescaler. The prescaler
clocks the subsequent CMOS flip-flop chain comprising the
fully programmable A and B counters.
1.3.2 Fractional Compensation
The fractional compensation circuitry of the LMX2354 RF
dividers allows the user to adjust the VCO’s tuning resolution
in 1/16 or 1/15 increments of the phase detector comparison
frequency. A 4-bit register is programmed with the fractions
desired numerator, while another bit selects between frac-
tional 15 and 16 modulo base denominator (see program-
ming description 5.2.3). An integer average is accomplished
by using a 4-bit accumulator. A variable phase delay stage
compensates for the accumulated integer phase error, mini-
mizing the charge pump duty cycle, and reducing spurious
levels. This technique eliminates the need for compensation
current injection in to the loop filter. Overflow signals gener-
ated by the accumulator are equivalent to 1 full VCO cycle,
and result in a pulse swallow.
1.4 PHASE/FREQUENCY DETECTOR
The RF and IF phase/frequency detectors are driven from
their respective N and R counter outputs. The phase detec-
tor outputs control the charge pumps. The polarity of the
pump-up or pump-down control is programmed using
RF_PD_POL or IF_PD_POL depending on whether RF/IF
VCO characteristics are positive or negative (see program-
ming descriptions 4.1.4 and 4.2.2). The phase detector also
receives a feedback signal from the charge pump, in order to
eliminate dead zone.
1.5 CHARGE PUMP
The phase detector’s current source outputs pump charge
into an external loop filter, which then converts the charge
into the VCO’s control voltage. The charge pumps steer the
charge pump output, CPo, to Vcc (pump-up) or ground
(pump-down).
When
locked,
CPo
is
primarily
in
a
TRI-STATE mode with small corrections. The RF charge
pump output current magnitude is programmable from
100 A to 1.6 mA in 100 A steps as shown in table in
programming description 4.2.2. The IF charge pump is set to
either 100 A or 800 A levels using bit IF_R [19] (see
programming description 4.1.4).
1.6 VOLTAGE DOUBLER
The V
pRF pin is normally driven from an external power
supply over a range of V
CC to 5.5V to provide current for the
RF charge pump circuit. An internal voltage doubler circuit
connected between the V
CC and VpRF supply pins alter-
nately allows V
CC =3V(±10%) users to run the RF charge
pump circuit at close to twice the V
CC power supply voltage.
The voltage doubler mode is enabled by setting the V2_EN
bit (RF_R [22]) to a HIGH level. The voltage doubler’s
charge pump driver originates from the RF oscillator input
(OSC
RF). The average delivery current of the doubler is less
than the instantaneous current demand of the RF charge
pump when active and is thus not capable of sustaining a
continuous out of lock condition. A large external capacitor
connected to V
pRF (≈0.1 F) is therefore needed to control
power supply droop when changing frequencies.
1.7 MICROWIRE SERIAL INTERFACE
The programmable functions are accessed through the MI-
CROWIRE serial interface. The interface is made of 3 func-
tions: clock, data and latch enable (LE). Serial data for the
various counters is clocked in from data on the rising edge of
clock, into the 24-bit shift register. Data is entered MSB first.
The last two bits decode the internal register address. On the
rising edge of LE, data stored in the shift register is loaded
into one of the 4 appropriate latches (selected by address
bits). A complete programming description is included in the
following sections.
LMX2354
www.national.com
11
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| LMX2354TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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| LMX2360 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2360TMX | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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