參數(shù)資料
型號(hào)： LMX2354SLDX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, CQCC24
封裝： LAMINATE, CSP-24
文件頁(yè)數(shù)： 7/26頁(yè)
文件大小： 453K
代理商： LMX2354SLDX
Programming Description (Continued)
4.2.1 (RF_R[22]–RF_R[23])
DLL_MODE
V2_EN
BIT
LOCATION
FUNCTION
0
1
DLL_MODE
RF_R [23]
Delay Line Loop
Calibration Mode
Slow
Fast
V2_EN
RF_R [22]
RF_Voltage Doubler
Enable
Disabled
Enabled
Note 1. V2_EN bit when set high enables the voltage doubler for the RF Charge Pump supply.
Note 2. DLL_MODE bit should be set to one for normal usage.
4.2.2 RF_CP_WORD
(RF_R[17]–RF_R[21])
CP_8X
CP_4X
CP_2X
CP_1X
RF_PD_POL
RF_PD_POL ( RF_R[17] ) should be set to one when RF VCO characteristics are positive. When RF VCO frequency decreases
with increasing control voltage RF_PD_POL should be set to zero.
CP_1X, CP_2X, CP_4X, and CP_8X are used to step the RF Charge Pump output current magnitude from 100 A to 1.6 mA in
100 A steps as shown in the table below.
RF Charge Pump Output Truth Table
ICPo A (typ)
CP8X
RF_R[21]
CP4X
RF_R[20]
CP2X
RF_R[19]
CP1X
RF_R[18]
100
0
200
0
1
300
0
1
0
400
0
1
900
1
0
1600
1
5.0 Programmable Dividers (N Counters)
5.1 IF_N REGISTER
If the Control Bits (CTL [1:0]) are 0 1, data is transferred from the 24-bit shift register into the IF_N register latch which sets the
PLL’s 15-bit programmable N counter value and various control functions. The IF_N counter consists of the 3-bit swallow counter
(A counter), and the 12-bit programmable counter (B counter). Serial data format is shown below in tables 5.1.3 and 5.1.4. The
divide ratio (IF_NB_CNTR) must be
≥ 3. The divide ratio is programmed using the bits IF_N_CNTR as shown in tables 5.1.2 and
5.1.3. The minimum continuous divide ratio is 56. The CMOS [3:0] bits program the 2 CMOS outputs detailed in section 5.1.2, and
also contain the fractional test bit.
MSB
LSB
IF_CTL_WORD [2:0]
CMOS [3:0]
IF_NB_CNTR [11:0]
IF_NA_CNTR [2:0]
0
1
23
21 20
17 16
5 4
2 1
0
5.1.1 IF_CTL_WORD
(IF_N[21]–IF_N[23])
MSB
LSB
IF_CNT_RST
PWDN_IF
PWDN_MODE
Note: See section 5.2.1.2 for IF control word truth table.
LMX2354
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參數(shù)描述
LMX2354SLEX 制造商:Texas Instruments 功能描述:
LMX2354TM 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Dual 10MHz to 2500MHz 24-Pin TSSOP Rail 制造商:Texas Instruments 功能描述:2.5GHZ/550MHZ PLL 2354 TSSOP24 制造商:Texas Instruments 功能描述:IC, DUAL FREQ SYNTHESIZER 2.5GHZ 24-TSSOP, PLL Type:Frequency Synthesis, Frequen
LMX2354TM 制造商:Texas Instruments 功能描述:2.5GHZ/550MHZ PLL 2354 TSSOP24
LMX2354TM/NOPB 功能描述:IC PLATINUM SYNTHESIZER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2354TMX/NOPB 功能描述:IC FREQ SYNTH 2.5GHZ 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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