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參數(shù)資料
| 型號： | LMX2354SLDX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, CQCC24 |
| 封裝： | LAMINATE, CSP-24 |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 453K |
| 代理商： | LMX2354SLDX |
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Programming Description (Continued)
4.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
(IF_R[2]–IF_R[16])
IF_R_CNTR/RF_R_CNTR
Divide
Ratio
14
13
12
11
10
987654321
0
3
00000000000001
1
4
00000000000010
0
32,767
11111111111111
1
Notes: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).
RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.
4.1.4 IF_CP_WORD
(IF_R[17]–IF_R[18])
CP_GAIN_8
IF_PD_POL
BIT
LOCATION
FUNCTION
0
1
CP_GAIN_8
IF_R [18]
IF Charge Pump
Current Gain
1X
8X
IF_PD_POL
IF_R [17]
IF Phase Detector
Polarity
Negative
Positive
CP_GAIN_8 is used to toggle the IF charge pump current magnitude between 1X mode (100 A typical) and 8X mode (800 A
typical).
IF_PD_POL is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control
voltage IF_PD_POL should set to 0.
4.1.5 FoLD* Programming Truth Table
(IF_R[19]–IF_R[21])
FoLD
Fo/LD OUTPUT STATE
0 0 0
IF and RF Analog Lock Detect
1 0 0
IF Digital Lock Detect
0 1 0
RF Digital Lock Detect
1 1 0
IF and RF Digital Lock Detect
0 0 1
IF R counter
1 0 1
IF N counter
0 1 1
RF R counter
1 1 1
RF N counter
*FoLD - Fout/Lock Detect PROGRAMMING BITS
4.2 RF_R Register
If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the
RF PLL’s 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 4.1.3. The
divide ratio must be
≥ 3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are
detailed in 4.2.2.
MSB
LSB
DLL_MODE
V2_EN
RF_CP_WORD [4:0]
RF_R_CNTR [14:0]
1
0
23
22 21
17 16
2 1
0
LMX2354
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| LMX2354TM/NOPB | 功能描述:IC PLATINUM SYNTHESIZER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2354TMX/NOPB | 功能描述:IC FREQ SYNTH 2.5GHZ 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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