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參數(shù)資料
| 型號： | LMX2352TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CAP,CER,DISC,RAD,100PF,10%,1KV |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO24 |
| 封裝： | PLASTIC, TSSOP-24 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2352TM |
Functional Description
1.0 General
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2350/52, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, as well as programmable reference
[R] and feedback [N] frequency dividers. The VCO frequency
is established by dividing the crystal reference signal down
via the R counter to obtain a frequency that sets the compari-
son frequency. This reference signal, fr, is then presented to
the input of a phase/frequency detector and compared with
another signal, fp, the feedback signal, which was obtained
by dividing the VCO frequency down by way of the N counter
and fractional circuitry. The phase/frequency detector’s cur-
rent source outputs pump charge into the loop filter, which
then converts the charge into the VCO’s control voltage. The
phase/frequency comparator’s function is to adjust the volt-
age presented to the VCO until the feedback signal’s fre-
quency (and phase) match that of the reference signal.
When this ’phase-locked’ condition exists, the RF VCO’s fre-
quency will be N+F times that of the comparison frequency,
where N is the integer divide ratio and F is the fractional
component. The fractional synthesis allows the phase detec-
tor frequency to be increased while maintaining the same
frequency step size for channel selection. The division value
N is thereby reduced giving a lower phase noise referred to
the phase detector input, and the comparison frequency is
increased allowing faster switching times.
1.1 Reference Oscillator Inputs
The reference oscillator frequency for the RF and IF PLL’s is
provided by either an external reference through the OSCin
pin and OSCx pin, or an external crystal resonator across
the OSCin and OSCx pins. OSCin/OSCx block can operate
to 50MHz with an input sensitivity of 0.5Vpp. The OSC bit
(see programming description 3.1.1), selects whether the os-
cillator input pins OSCin and OSCx drive the IF and RF R
counters separately (Low) or by a common input signal path
(Hi). The common OSC mode allows the user to form a local
crystal oscillator circuit or drive the OSCin pin from an exter-
nal signal source. When a crystal resonator is connected be-
tween OSCin and OSCx along with 2 external capacitors to
form a crystal oscillator both reference chains are driven si-
multaneously. When a TCXO is connected only at the OSCin
input pin and not at the OSCx pin, the TCXO drives both IF
R counter and RF R counter. When configured as separate
inputs, the OSCin pin drives the IF R counter while the OSCx
drives the RF R counter. The inputs have a Vcc/2 input
threshold and can be driven from an external CMOS or TTL
logic gate.
1.2 Reference Dividers (R Counters)
The RF and IF R Counters are clocked through the oscillator
block either separately or in common. The maximum fre-
quency is 50MHz. Both R Counters are 15 bit CMOS
counters with a divide range from 3 to 32,767. (See program-
ming description 3.1.3.)
1.3 Programmable Dividers (N Counters)
The RF and IF N Counters are clocked by the small signal fin
RF and fin IF input pins respectively. The LMX2350 RF N
counter is 19 bits with 15 bits integer divide and 4 bits frac-
tional. The integer part is configured as a 5 bitACounter and
a 10 bit B Counter. The LMX2350 is capable of operating
from 500 MHz to 1.2 GHz with the 16/17 prescaler offering a
continuous integer divide range from 272 to 16399, and 1.2
GHz to 2.5 GHz with the 32/33 prescaler offering a continu-
ous integer divide range from 1056 to 32767. The LMX2352
RF N counter is 18 bits with 14 bits integer divide and 4 bits
fractional. The integer part is configured as a 4 bit A Counter
and a 10 bit B Counter. The LMX2352 is capable of operat-
ing from 250 MHz to 500 MHz with the 8/9 prescaler offering
a continuous integer divide range from 72 to 8199, and
500MHz to 1.2 GHz with 16/17 prescaler offering a continu-
ous integer divide range from 272 to 16383. The RF
counters for the LMX2350 family also contain fractional com-
pensation, programmable in either 1/15 or 1/16 modes. Both
LMX2350 and LMX2352 IF N counters are 15 bit integer di-
viders configured with a 3 bit A Counter and a 12 bit B
Counter offering a continuous integer divide range from 56 to
32,767 over the frequency range of 10 MHz to 550 MHz. The
IF N counters do not include fractional compensation.
1.3.1 Prescaler
The RF and IF inputs to the prescaler consist of fin and /fin;
which are complimentary inputs to differential pair amplifiers.
The complimentary inputs are internally coupled to ground
with a 10 pF capacitor. These inputs are typicallyAC coupled
to ground through external capacitors as well. The input
buffer drives the A counter’s ECL D-type flip flops in a dual
modulus configuration. A 16/17 or 32/33 prescale ratio can
be selected for the LMX2350, and the lower frequency
LMX2352 provides 8/9 or 16/17 prescale ratios. The IF cir-
cuitry for both the LMX2350 and LMX2352 contain an 8/9
prescaler. The prescaler clocks the subsequent CMOS flip-
flop chain comprising the fully programmable A and B
counters.
1.3.2 Fractional Compensation
The fractional compensation circuitry of the LMX2350 and
LMX2352 RF dividers allow the user to adjust the VCO’s tun-
ing resolution in 1/16 or 1/15 increments of the phase detec-
tor comparison frequency. A 4 bit register is programmed
with the fractions desired numerator, while another bit se-
lects between fractional 15 and 16 modulo base denomina-
tor (see programming description 4.2.4). An integer average
is accomplished by using a 4 bit accumulator. A variable
phase delay stage compensates for the accumulated integer
phase error, minimizing the charge pump duty cycle, and re-
ducing spurious levels. This technique eliminates the need
for compensation current injection in to the loop filter. Over-
flow signals generated by the accumulator are equivalent to
1 full VCO cycle, and result in a pulse swallow.
1.4 Phase/Frequency Detector
The RF and IF phase(/frequency) detectors are driven from
their respective N and R counter outputs. The maximum fre-
quency at the phase detector inputs is about 2 MHz for some
high frequency VCO due to the minimum continuous divide
ratio of the dual modulus prescaler (i.e. If the VCO output fre-
quency is 2.4816 GHz, the maximum phase detector input
frequency is 2.35 MHz because the minimum continuous di-
vide ratio of the LMX2350 with 32/33 prescaler is 1056). The
phase detector outputs control the charge pumps. The polar-
ity of the pump-up or pump-down control is programmed us-
ing RF_PD_POL or IF_PD_POL depending on whether
RF/IF VCO characteristics are positive or negative (see pro-
gramming descriptions 3.1.4 and 3.2.2). The phase detector
also receives a feedback signal from the charge pump, in or-
der to eliminate dead zone.
www.national.com
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| LMX2352TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2352TMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial-Input Frequency Synthesizer |
| LMX2352TMX/NOPB | 功能描述:IC FREQUENCY SYNTHESIZER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2353 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Fractional N Single 2.5 GHz Frequency Synthesizer |
| LMX2353SLBX | 功能描述:IC FREQ SYNTH 2.5GHZ 16LAMCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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