- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384604 > LMX2350 (National Semiconductor Corporation) PLLatinum Fractional Dual Low Power Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) PDF資料下載
參數(shù)資料
| 型號： | LMX2350 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Fractional Dual Low Power Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) |
| 中文描述： | PLLatinum分數(shù)雙低功耗頻率合成器（PLLatinum技術(shù)低耗雙通道頻率合成器） |
| 文件頁數(shù)： | 15/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2350 |
Programming Description
(Continued)
4.1.2 3-BIT IF SWALLOW COUNTER DIVIDE RATIO (IF A COUNTER)
(IF_N[2][4])
Swallow Count
(A)
0
1
-
7
IF_NA_CNTR
1
0
0
-
1
2
0
0
-
1
0
0
1
-
1
Note:
Swallow Counter Value: 0 to 7
IF_NB_CNTR
≥
IF_NA_CNTR
Minimum continuous count = 56 ( A=0, B=7)
4.1.3 12-BIT IF PROGRAMMABLE COUNTER DIVIDE RATIO (IF B COUNTER)
(IF_N[5]-[16])
IF_NB_CNTR
7
0
0
-
1
Divide Ratio
3
4
-
4,095
Note:
Divide ratio: 3 to 4095 (Divide ratios less than 3 are prohibited)
IF_NB_CNTR
≥
IF_NA_CNTR
N divider continuous integer divide ratio 56 to 32,767.
11
0
0
-
1
10
0
0
-
1
9
0
0
-
1
8
0
0
-
1
6
0
0
-
1
5
0
0
-
1
4
0
0
-
1
3
0
0
-
1
2
0
1
-
1
1
1
0
-
1
0
1
0
-
1
4.2 RF_N Register
If the control bits (CTL[2:0]) are 11, data is transferred from the 24-bit shift register into the RF_N register latch which sets the RF
PLL 19 bit programmable N counter register and various control functions. The RF N counter consists of the 5-bit swallow counter
(A counter) the 10 bit programmable counter (B counter), and 4 bit fractional counter. Serial data format is shown below. The di-
vide ratio (RF_NB_CNTR) must be
≥
3, and must be
≥
the swallow counter value + 2; RF_NB_CNTR
≥
( RF_NA_CNTR+2).
MSB
RF_CTL_WORD [2:0]
23
LSB
RF_NB_CNTR [9:0]
20
RF_NA_CNTR [4:0]
10
FRAC_CONT [3:0]
5
1
1
1
0
21
11
6
2
4.2.1.1 RF_CTL_WORD
(RF_N[21]-[23])
MSB
RF_CNT_RST
LSB
PWDN_RF
PRESC_SEL
4.2.1.2 RF/IF Control Word Truth Table
BIT
FUNCTION
0
1
IF_CNT_RST/RF_CNT_RST
PWDN_IF/PWDN_RF
PWDN_MODE
PRESC
IF/RF counter reset
IF/RF power down
Power down mode select
Prescaler Modulus select
Normal Operation
Powered up
Asynchronous power down
16/17
(0.5 to 1.2 GHz operation)
8/9
(0.25 to 0.5 GHz operation)
Reset
Powered down
Synchronous power down
32/33
(1.2 to 2.5 GHz operation)
16/17
(0.5 to 1.2 GHz operation)
LMX2350
LMX2352
The
Counter Reset
enable bit when activated allows the re-
set of both N and R counters. Upon powering up, the N
counter resumes counting in
″
close
″
alignment with the R
counter (the maximum error is one prescaler cycle).
Activation of the PLL
power down
bits result in the disabling
of the respective N counter divider and de-biasing of its re-
spective fin inputs (to a high impedance state). The respec-
tive R counter functionality also becomes disabled when the
power down bit is activated. The OSCin pin reverts to a high
impedance state when both RF and IF power down bits are
asserted. Power down forces the respective charge pump
and phase comparator logic to a TRI-STATE condition. The
MICROWIRE control register remains active and capable of
loading and latching in data during all of the power down
modes.
Both synchronous and asynchronous power down modes
are available with the LMX2350 family in order to adapt to
different types of applications. The power down mode bit
IF_N[21] is used to select between synchronous and asyn-
chronous power down. The MICROWIRE control register re-
mains active and capable of loading and latching in data dur-
ing all of the power down modes.
www.national.com
15
相關PDF資料 |
PDF描述 |
|---|---|
| LMX2352 | PLLatinum Fractional Dual Low Power Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) |
| LMX2350TM | PLLatinum⑩ Fractional N RF / Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2352TM | CAP,CER,DISC,RAD,100PF,10%,1KV |
| LMX2470 | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
| LMX2470SLEX | 2.6 GHz Delta-Sigma Fractional-N PLL with 800 MHz Integer-N PLL |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2350SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2350TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum TM Fractional N RF / Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2350TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2350TMB | 制造商:Texas Instruments 功能描述: |
| LMX2350TMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial-Input Frequency Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復。