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參數(shù)資料
| 型號： | LMX2350 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Fractional Dual Low Power Frequency Synthesizer(PLLatinum技術(shù)低耗雙通道頻率合成器) |
| 中文描述： | PLLatinum分?jǐn)?shù)雙低功耗頻率合成器（PLLatinum技術(shù)低耗雙通道頻率合成器） |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 378K |
| 代理商： | LMX2350 |
Programming Description
(Continued)
3.1.3 15-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO (R COUNTER)
(IF_R[2]-[16])
IF_R_CNTR/RF_R_CNTR
10
9
0
0
0
0
-
-
1
1
Divide Ratio
3
4
-
32,767
14
0
0
-
1
13
0
0
-
1
12
0
0
-
1
11
0
0
-
1
8
0
0
-
1
7
0
0
-
1
6
0
0
-
1
5
0
0
-
1
4
0
0
-
1
3
0
0
-
1
2
0
1
-
1
1
1
0
-
1
0
1
0
-
1
Notes: Divide ratio: 3 to 32,767 (Divide ratios less than 3 are prohibited).
RF_R_CNTR/IF_R_CNTR These bits select the divide ratio of the programmable reference dividers.
3.1.4 IF_CP_WORD
(IF_R[17]-[18])
IF_CP_WORD
CP_GAIN_8
(IF_R [17] - [18] )
IF_PD_POL
BIT
CP_GAIN_8
IF_PD_POL
CP_GAIN_8
is used to toggle the IF charge pump current magnitude between 1x mode (100 uA typ) and 8x mode (800uA typ).
IF_PD_POL
is set to one when IF VCO characteristics are positive. When IF VCO frequency decreases with increasing control
voltage IF_PD_POL should set to zero.
LOCATION
IF_R [18]
IF_R [17]
FUNCTION
IF Charge Pump Current Gain
IF Phase Detector Polarity
0
1X
Negative
1
8X
Positive
3.1.5 FoLD* Programming Truth Table
(IF_R[19]-[21])
FoLD
0 0 0
1 0 0
0 1 0
1 1 0
0 0 1
1 0 1
0 1 1
1 1 1
Fo/LD OUTPUT STATE
IF and RF Analog Lock Detect (Open Drain)
IF Digital Lock Detect
RF Digital Lock Detect
IF and RF Digital Lock Detect
IF R counter
IF N counter
RF R counter
RF N counter
*FoLD - Fout/Lock Detect PROGRAMMING BITS
3.2 RF_R Register
If the Control Bits (CTL [1:0]) are 1 0, data is transferred from the 24-bit shift register into the RF_R register latch which sets the
RF PLL 15-bit R counter divide ratio. The divide ratio is programmed using the RF_R_CNTR word as shown in table 3.1.3. The
divide ratio must be
≥
3. The bits used to control the voltage doubler (V2_EN) and RF Charge Pump (RF_CP_WORD) are de-
tailed in 3.2.2.
MSB
DLL_MODE
23
LSB
0
0
V2_EN
RF_CP_WORD [4:0]
21
RF_R_CNTR [14:0]
16
1
1
22
17
2
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| LMX2350TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum TM Fractional N RF / Integer N IF Dual Low Power Frequency Synthesizer |
| LMX2350TM/NOPB | 功能描述:IC FREQ SYNTHESIZER DUAL 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2350TMB | 制造商:Texas Instruments 功能描述: |
| LMX2350TMX | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Serial-Input Frequency Synthesizer |
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