參數(shù)資料
型號: LMX2336MDA
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 2000 MHz, UUC
封裝: DIE
文件頁數(shù): 9/25頁
文件大小: 578K
代理商: LMX2336MDA
Application Information (Continued)
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX2335L/36L PLL is shown in
Fig-
ure 5. When a new frequency is loaded, and the RF1 I
CPo bit
is set high, the charge pump circuit receives an input to de-
liver 4 times the normal current per unit phase error while an
open drain NMOS on chip device switches in a second R2
resistor element to ground. The user calculates the loop filter
component values for the normal steady state consider-
ations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability con-
siderations to account for. Once locked on the correct fre-
quency, the user can return the PLL to standard low noise
operation by sending a MICROWIRE instruction with the
RF1 I
CPo bit set low. This transition does not affect the
charge on the loop filter capacitors and is enacted synchro-
nous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
DS012807-16
FIGURE 4. Open Loop Response Bode Plot
DS012807-17
FIGURE 5. Fastlock PLL Architecture
www.national.com
17
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相關代理商/技術參數(shù)
參數(shù)描述
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