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參數(shù)資料
| 型號： | LMX2336MDA |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 8/25頁 |
| 文件大小： | 578K |
| 代理商： | LMX2336MDA |
Application Information
A block diagram of the basic phase locked loop is shown in
Figure 1.
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in
Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
VCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in
Figure 3, WHILE
the complex impedance of the filter is given in equation 2.
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω, the filter time contants T1 and T2, and
the design constants K
φ,K
VCO, and N.
(4)
From
Equation (3) we can see that the phase term will be de-
pendent on the single pole and zero such that the phase
margin is determined in
Equation (1).
φ(ω) = tan1 (ω T2) tan1 (ω T1) + 180C
(5)
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in
Equation (4) with a solid trace. The param-
eter
φ
p shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison fre-
quency also diminishes, the spurs would have increased by
approximately 6 dB. In the proposed Fastlock scheme, the
higher spur levels and wider loop filter conditions would exist
only during the initial lock-on phase — just long enough to
reap the benefits of locking faster. The objective would be to
open up the loop bandwidth but not introduce any additional
complications or compromises related to our original design
criteria. We would ideally like to momentarily shift the curve
Figure 4 over to a different cutoff frequency, illustrated by
dotted line, without affecting the relative open loop gain and
phase relationships. To maintain the same gain/phase rela-
tionship at twice the original cutoff frequency, other terms in
the gain and phase equations 4 and 5 will have to compen-
sate by the corresponding “1/w” or “1/w
2” factor. Examination
of equations 3 and 5 indicates the damping resistor variable
R2 could be chosen to compensate with “w” terms for the
phase margin. This implies that another resistor of equal
value to R2 will need to be switched in parallel with R2 during
the initial lock period. We must also insure that the magni-
tude of the open loop gain, H(s)G(s) is equal to zero at wp’ =
2 wp. K
VCO,Kφ, N, or the net product of these terms can be
changed by a factor of 4, to counteract with w
2 term present
in the denominator of equation 3. The K
φ term was chosen to
complete the transformation because it can readily be
switched between 1X and 4X values. This is accomplished
by increasing the charge pump output current from 1 mA in
the standard mode to 4 mA in Fastlock.
DS012807-13
FIGURE 1. Conventional PLL Architecture
DS012807-14
FIGURE 2. PLL Linear Model
DS012807-15
FIGURE 3. Passive Loop Filter
www.national.com
16
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2336TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336TMX | 功能描述:IC FREQ SYNTH DL 1.1GHZ 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| LMX2336U | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336U WAF | 制造商:Texas Instruments 功能描述: |
| LMX2336USLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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