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參數(shù)資料
| 型號： | LMX2336LTMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 631K |
| 代理商： | LMX2336LTMX/NOPB |
Application Information (Continued)
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase — just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve Figure 4 over to a different cutoff frequency, illustrated
by dotted line, without affecting the relative open loop gain
and phase relationships. To maintain the same gain/phase
relationship at twice the original cutoff frequency, other terms
in the gain and phase equations 4 and 5 will have to com-
pensate by the corresponding “1/w” or “1/w
2” factor. Exami-
nation of equations 3 and 5 indicates the damping resistor
variable R2 could be chosen to compensate with “w” terms
for the phase margin. This implies that another resistor of
equal value to R2 will need to be switched in parallel with R2
during the initial lock period. We must also insure that the
magnitude of the open loop gain, H(s)G(s) is equal to zero at
wp’ = 2 wp. K
VCO,K
φ, N, or the net product of these terms
can be changed by a factor of 4, to counteract with w
2 term
present in the denominator of equation 3. The K
φ term was
chosen to complete the transformation because it can
readily be switched between 1X and 4X values. This is
accomplished by increasing the charge pump output current
from 1 mA in the standard mode to 4 mA in Fastlock.
Fastlock Circuit Implementation
A diagram of the Fastlock scheme as implemented in Na-
tional Semiconductors LMX2335L/36L PLL is shown in Fig-
ure 5. When a new frequency is loaded, and the RF1 I
CPo bit
is set high, the charge pump circuit receives an input to
deliver 4 times the normal current per unit phase error while
an open drain NMOS on chip device switches in a second
R2 resistor element to ground. The user calculates the loop
filter component values for the normal steady state consid-
erations. The device configuration ensures that as long as a
second identical damping resistor is wired in appropriately,
the loop will lock faster without any additional stability con-
siderations to account for. Once locked on the correct fre-
quency, the user can return the PLL to standard low noise
operation by sending a MICROWIRE instruction with the
RF1 I
CPo bit set low. This transition does not affect the
charge on the loop filter capacitors and is enacted synchro-
nous with the charge pump output. This creates a nearly
seamless change between Fastlock and standard mode.
01280716
FIGURE 4. Open Loop Response Bode Plot
01280717
FIGURE 5. Fastlock PLL Architecture
LMX2335L/LMX2336L
www.national.com
19
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| LMX2336LTM/NOPB | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
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| LMX2335UM | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16 |
| LMX2336USLB | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24 |
| LMX2335UTM/NOPB | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2336TM | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336TMX | 功能描述:IC FREQ SYNTH DL 1.1GHZ 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2336U | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2336U WAF | 制造商:Texas Instruments 功能描述: |
| LMX2336USLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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