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參數資料
| 型號： | LMX2335UTMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數： | 35/48頁 |
| 文件大?。?/td> | 3127K |
| 代理商： | LMX2335UTMX |
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1.0 Functional Description
(Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (ID
RF1 Bit = 0) in the steady state mode, to
3.8 mA (ID
RF1 Bit = 1) in Fastlock. When the F
LD output
is configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 F
o
LD
for details on how to configure the F
o
LD
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the F
LD is programmed to
Reset RF2 Counters
, both the
RF2 feedback divider and the RF2 reference divider are held
at their load point. When the
Reset RF1 Counters
is pro-
grammed, both the RF1 feedback divider and the RF1 ref-
erence divider are held at their load point. When the
Reset
All Counters
mode is enabled, all feedback dividers and
reference dividers are held at their load point. When the
device is programmed to normal operation, both the feed-
back divider and reference divider are enabled and resume
counting in ‘close’ alignment to each other. Refer to
Section
2.8 F
o
LD
for more details.
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R dividers can be moni-
tored by selecting the appropriate F
LD word. This is essen-
tial when performing OSC
or f
sensitivity measurements.
Refer to the
Test Setups
section for more details. Refer to
Section 2.8 F
LD
for more details on how to route the
appropriate divider output to the F
o
LD pin.
1.9 POWER CONTROL
Each synthesizer in the LMX2335U or LMX2336U is indi-
vidually power controlled by device powerdown bits. The
powerdown word is comprised of the
PWDN RF1
(
PWDN
RF2
) bit, in conjuction with the
TRI-STATE ID
RF1
(
TRI-STATE ID
RF2
) bit. The powerdown control word is
used to set the operating mode of the device. Refer to
Sections 2.4.4, 2.5.4, 2.6.4
, and
2.7.4
for details on how to
program the RF1 or RF2 powerdown bits.
When either the RF1 synthesizer or the RF2 synthesizer
enters the powerdown mode, the respective prescaler,
phase detector, and charge pump circuit are disabled. The
D
RF1 (D
RF2), f
RF1 (f
RF2), and f
RF1 (f
RF2)
pins are all forced to a high impedance state. The reference
divider and feedback divider circuits are held at the load
point during powerdown. The oscillator buffer is disabled
when both the RF1 and RF2 synthesizers are powered
down. The OSC
pin is forced to a HIGH state through an
approximate 100 k
resistance when this condition exists.
When either synthesizer is activated, the respective pres-
caler, phase detector, charge pump circuit, and the oscillator
buffer are all powered up. The feedback divider, and the
reference divider are held at load point. This allows the
reference oscillator, feedback divider, reference divider and
prescaler circuitry to reach proper bias levels. After a finite
delay, the feedback and reference dividers are enabled and
they resume counting in ‘close’ alignment (the maximum
error is one prescaler cycle). The MICROWIRE control reg-
ister remains active and capable of loading and latching data
while in the powerdown mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
TRI-STATE ID
o
0
1
0
1
PWDN
0
0
1
1
Operating Mode
PLL Active, Normal Operation
PLL Active, Charge Pump Output in High Impedance State
Synchronous Powerdown
Asynchronous Powerdown
Notes:
1. TRI-STATE ID
o
refers to either the TRI-STATE ID
o
RF1 or TRI-STATE ID
o
RF2 bit .
2. PWDN refers to either the PWDN RF1 or PWDN RF2 bit.
L
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| LMX2336 WAF | 制造商:Texas Instruments 功能描述: |
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| LMX2336LSLBX | 功能描述:IC PLLANTINUM SYNTHESZR LAM CSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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