參數(shù)資料
型號(hào): LMX2332UTMX/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20
封裝: 0.173 INCH, PLASTIC, TSSOP-20
文件頁數(shù): 28/49頁
文件大?。?/td> 4568K
代理商: LMX2332UTMX/NOPB
Test Setups (Continued)
LMX233xU OSC
in Sensitivity Test Setup
10136641
The block diagram above illustrates the setup required to
measure the LMX233xU device’s OSC
in buffer sensitivity
level. The same setup is used for the LMX2330TMEB/
LMX2330SLEEB Evaluation Boards. This setup is similar to
the f
IN sensitivity setup except that the signal generator is
now connected to the OSC
in pin and both fIN pins are tied to
V
CC. The 51
shunt resistor matches the OSC
in input to the
signal generator. The R counter is typically set to 1000, i.e.
RF R_CNTR Word = 1000 or IF R_CNTR Word = 1000. The
reference divider output is routed to the F
oLD pin by select-
ing the RF PLL R Divider Output word (F
oLD Word = 2 or
10) or the IF PLL R Divider Output word (F
oLD Word = 1 or
9) in Code Loader. Similarly, a Universal Counter is con-
nected to the F
oLD pin and is tied to the 10 MHz reference
output from the signal generator. The output of the reference
divider is monitored and should be equal to OSC
in/RF
R_CNTR or OSC
in/ IF R_CNTR.
Again, V
CC is swept from 2.7V to 5.5V. The OSCin input
frequency and voltage level are then swept with the signal
generator. The measurements are repeated at different tem-
peratures, namely T
A = -40C, +25C, and +85C. Sensitivity
is reached when the frequency error of the divided input
signal is greater than or equal to 1 Hz.
LMX2330U/LMX2331U/LMX2332U
www.national.com
34
相關(guān)PDF資料
PDF描述
LMX2332UTM/NOPB PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO20
LMX2331UTM/NOPB PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20
LMX2331USLEX PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24
LMX2330UTMX/NOPB PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20
LMX2335LTMX/NOPB PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16
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