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參數(shù)資料
| 型號： | LMX2324ATM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 157K |
| 代理商： | LMX2324ATM |
2.0 Programming Description (Continued)
2.3.4.1 Control Word Truth Table
CE
CNT_RST
PWDN
Function
1
0
Normal Operation
1
0
1
Synchronous Powerdown
1
0
Counter Reset
1
Asynchronous Powerdown
0
X
Asynchronous Powerdown
Notes: X denotes don’t care.
The Counter Reset enable bit when activated allows the reset of both N and R counters. Upon powering up the N counter
resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle).
Both synchronous and asynchronous power down modes are available with the LMX2324A to be able to adapt to different types
of applications. The MICROWIRE control register remains active and capable of loading and latching in data during all of the
powerdown modes.
Synchronous Power down Mode
The PLL loops can be synchronously powered down by setting the counter reset mode bit to LOW (N[1] = 0) and its power down
mode bit to HIGH (N[0] = 1). The power down function is gated by the charge pump. Once the power down mode and counter
reset mode bits are loaded, the part will go into power down mode upon the completion of a charge pump pulse event.
Asynchronous Power down Mode
The PLL loops can be asynchronously powered down by setting the counter reset mode bit to HIGH (N[1] = 1) and its power down
mode bit to HIGH (N[0] = 1), or by setting CE pin LOW. The power down function is NOT gated by the charge pump. Once the
power down and counter reset mode bits are loaded, the part will go into power down mode immediately.
The R and N counters are disabled and held at load point during the synchronous and asynchronous power down modes. This
will allow a smooth acquisition of the RF signal when the PLL is programmed to power up. Upon powering up, both R and N
counters will start at the ‘zero’ state, and the relationship between R and N will not be random.
Serial Data Input Timing
DS101246-5
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
Test Conditions: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 1.6V @ VCC = 2.7V and 3.3V @ VCC = 5.5V.
LMX2324A
www.national.com
9
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