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參數(shù)資料
| 型號(hào)： | LMX2324ATM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2200 MHz, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 157K |
| 代理商： | LMX2324ATM |
2.0 Programming Description (Continued)
2.1.2 Register Content Truth Table
MSB
SHIFT REGISTER BIT LOCATION
LSB
17
16
15
14
13
12
11
10
9
8
7654
3
2
1
0
Register
Data Field
ADDR Field
N
NB_CNTR[9:0]
NA_CNTR[4:0]
CTL_WORD[1:0]
0
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
R
X
TEST
RS
PD_
POL
CP_
TRI
R_CNTR[9:0]
1
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
2.2 R REGISTER
If the Address Bit (ADDR) is 1, when LE is transitioned high data is transferred from the 18-bit shift register into the 14-bit R
register. The R register contains a latch which sets the PLL 10-bit R counter divide ratio. The divide ratio is programmed using
the bits R_CNTR as shown in table 2.2.1. The ratio must be
≥ 2. The PD_POL, CP_TRI and TEST bits control the phase detector
polarity, charge pump TRI-STATE, and test mode respectively, as shown in 2.2.2. The RS bit is reserved and should always be
set to zero. X denotes a don’t care condition. Data is clocked into the shift register MSB first.
MSB
SHIFT REGISTER BIT LOCATION
LSB
17
16
15
14
13
12
11
10
987654
3
2
1
0
Register
Data Field
ADDR Field
R
X
TEST
RS
PD_
POL
CP_
TRI
R_CNTR[9:0]
1
R16
R15
R14
R13
R12
R11
R10
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
2.2.1 10-Bit Programmable Reference Divider Ratio (R Counter)
R_CNTR[9:0]
Divide Ratio
R9
R8
R7
R6
R5
R4
R3
R2
R1
R0
2
0000000010
3
0000000011
1,023
1111111111
Notes: Divide ratio: 2 to 1,023 (Divide ratios less than 2 are prohibited)
R_CNTR — These bits select the divide ratio of the programmable reference dividers.
2.2.2 R Register Truth Table
Bit
Location
Function
0
1
CP_TRI
R[10]
Charge Pump TRI-STATE
Normal Operation
TRI-STATE
PD_POL
R[11]
Phase Detector Polarity
Negative
Positive
TEST
R[13]
Test Mode Bit
Normal Operation
Test Mode
If the test mode is NOT activated (R[13]=0), the charge pump is active when CP_TRI is set LOW. When CP_TRI is set HIGH, the
charge pump output and phase comparator are forced to a TRI-STATE condition. This bit must be set HIGH if the test mode is
ACTIVATED (R[13]=1).
If the test mode is NOT activated (R[13]=0), PD_POL sets the VCO characteristics to positive when set HIGH. When PD_POL
is set LOW, the VCO exhibits a negative characteristic where the VCO frequency decreases with increasing control voltage.
If the test mode is ACTIVATED (R[13]=1), the outputs of the N and R counters are directed to the CP
o output to allow for testing.
The PD_POL bit selects which counter output according to Table 2.2.3.
2.2.3 Test Mode Truth Table (R[13] = 1)
CP
o Output
CP_TRI R[10]
PD_POL R[11]
R Divider Output
1
0
N Divider Output
1
LMX2324A
www.national.com
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