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參數(shù)資料
| 型號(hào)： | LMX2322 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinumTM 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLLatinumTM 2.0千兆赫頻率合成射頻個(gè)人通信 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大?。?/td> | 227K |
| 代理商： | LMX2322 |
LMX2322
Electrical Characteristics
Vcc = 3.75, Vp = 3.75V ; -40oC <TA< 85oC except as specified
Symbol
Parameter
Advance Information
Rev 1.6
9/24/1998
4
Condition
Min
Typ
Max
Unit
Icc
Power Supply Current
Vcc = 3.75 V
3.5
mA
Icc
Vcc=2.7V to 3.9V
7.0
mA
Icc-
PWDN
Vcc = 3.9V (Note 1)
10
20
μ
A
μ
A
GHz
Vcc = 3.9V (Note 2)
300
f
in
RF Operating Frequency
0.7
2.0
f
osc
Oscillator Frequency
5
13
40
MHz
f
φ
V
f
in
Phase Detector Frequency
0.2
10
MHz
Input Sensitivity
Vcc = 2.7 to 3.9 V
Balanced input
f=900MHz (Note 3)
45
450
mV
RMS
Zin
Input Impedance
130
360
Vpp
f=1900MHz (Note 3)
100
150
Vosc
Oscillator Sensitivity
OSCin
0.4
0.8
1.2
Phase Noise (Note 4)
Fin=900MHz, Vosc>=0.8Vpp
-86
Note 6
dBc/Hz
Fin=900MHz, Vosc>=0.4Vpp
-82
Note 6
Fin=1800MHz, Vosc>=0.8Vpp
-82
Note 6
Fin=1800MHz, Vosc>=0.4Vpp
-80
Note 6
V
IH
High-level Input Voltage
(Note 5)
2.5
V
V
IL
Low-level Input Voltage
(Note 5)
0.4
V
I
IH
High-level Input Current (Clock, Data,
Load Enable)
Low-level Input Current (Clock, Data,
Load Enable)
Oscillator Input Current
V
IH
= Vcc = 3.9 V
-1.0
1.0
μ
A
I
IL
V
IL
= 0, Vcc = 3.9 V
-1.0
1.0
μ
A
I
IH
V
IH
= Vcc = 3.9 V
100
uA
I
IL
V
IL
= 0, Vcc = 3.9 V
-100
uA
I
CPo-source
Charge Pump Output Current
V
CPo
= Vp/2
-4.0
mA
I
CPo-sink
V
CPo
= Vp/2
4.0
mA
I
CPo-Tri
Charge Pump Tri-State Current
0.5 < V
CPo
< Vp - 0.5
T= 25
o
C
0.5 < V
CPo
< Vp - 0.5
T = 25
o
C
V
CPo
= Vp/2
T = 25
o
C
V
CPo
= Vp/2
-40
o
C < T < +85
o
C
-2.5
0.1
2.5
nA
I
CPo vs
V
CPo
I
CPo-sink vs.
I
CPo-source
I
CPo vs.
T
Charge Pump Output Current
magnitude variation vs. Voltage
Charge Pump Output Current
Sink vs. Source Mismatch
Charge Pump Output Current
Magnitude Variation vs. Temperature
(Note 4)
Data to Clock Set Up Time
10
%
5
%
8
%
t
CS
See Data Input Timing
50
ns
t
CH
Data to Clock Hold Time
See Data Input Timing
10
ns
t
CWH
Clock Pulse Width High
See Data Input Timing
50
ns
t
CWL
Clock Pulse Width Low
See Data Input Timing
50
ns
t
ES
Clock to Enable Set Up Time
See Data Input Timing
50
ns
t
EW
Enable Pulse Width
See Data Input Timing
50
ns
Note 1: This Icc-PWDN represents CLK, DATA, LE and CE being tied to either higher than 0.8Vcc or lower than 0.2Vcc.
Note 2: This Icc-PWDN represents a software power down condition of CE = VIH = 2.5V while LE, CLK and DATA = VIL = 0.4V. Worst case Icc-PWDN of 300
μ
A
occurs when CE, LE, CLK and DATA are all held at VIH = 2.5V (4x75
μ
A).
Note 3: Balanced input, | Z | = | R - jXc |
Note 4: Phase noise is measured 1kHz off from the carrier frequency. Comparison frequency is 200kHz. OSCin frequency is 13MHz.
Note 5: except fin and OSCin
Note 6: Typical values are determined from measurements on the reference evaluation boards. A 3dB (3 sigma) degradation is estimated from statistical
distribution in manufacturing. Units will NOT be tested in production.
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| LMX2322 WAF | 制造商:Texas Instruments 功能描述: |
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| LMX2323 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum? 2.0 GHz Frequency Synthesizer for RF Personal Communications |
| LMX2323 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2323TMX | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Texas Instruments 功能描述: |
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