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參數(shù)資料
| 型號： | LMX2316TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, PDSO16 |
| 封裝： | 0.173 INCH, LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 8/19頁 |
| 文件大小： | 342K |
| 代理商： | LMX2316TMX/NOPB |
2.0 Application Information
(Continued)
2.6 N COUNTER
The calculated value of N, and the value of P are now used
to determine the values of A and B where A and B are both
integer values:
N=P *B+ A
where B is the divisor and A is the remainder. Therefore:
B = div (N/P)
and
A =N(B*P)
For this example, B and A are calculated as follows:
B = div (4750/32) = 148 = 0000010010100
and
A = 4750(148*32)=14=01110
To load the N counter with these values, the programming bit
stream would be as follows. The first bit, the GO bit, (MSB)
N[19] is used for FastLock operation and will be discussed in
the F Latch section. The next 13 bits, (N[18]–N[6]) shifted in,
are the B counter value, 0000010010100
b *. Bits N[5]–N[1]
are the A counter and are 01110
b in this example. The final
two bits (the control bits) are 1,0 identifying the N counter. In
programming the N counter, the value of B must be greater
than or equal to A, and the value of B must be greater than
or equal to 3.
Note: *In programming the counter, data is shifted in MSB first.
10012714
2.7 R COUNTER
Programming the R counter is done by shifting in the binary
value of R calculated previously (50
d = 110010b). The first bit
shifted in is R[19] the LD precision bit. The next 4 bits
(R[18]–R[15]) shifted in, are used for testing and should
always be loaded with zeros. The R[14]–R[1] bits are used to
program
the
reference
divider
ratio
and
should
be
00000000110010
b for this example. The final two bits, C[1]
and C[2] denote the R counter and should be 0, 0. The
resulting bit stream looks as follows:
10012716
2.8 F LATCH
To program the device for any of the FastLock modes, C[1] =
0 and C[2] = 1 which direct data to the F latch. The Section
1.3 FUNCTION AND INITIALIZATION LATCH section dis-
cusses the 4 modes of FastLock operation. The user must
first determine which FastLock mode will be used. When
using any of the FastLock modes, the programmer needs to
experimentally determine the length of time to stay in high
gain mode. This is done by looking at the transient response
and determining the time at which the device has settled to
within the appropriate frequency tolerance. FastLock mode
should be terminated just prior to “l(fā)ock” to place the switch-
ing phase glitch within the transient settling time. The
counter reset mode (F[1] bit) holds both the N and R
counters at load point when F[1] = HIGH. Upon setting F[1]
= LOW, the N and R counters will resume counting in close
phase alignment. Other functions of the F latch such as
FoLD output control, Phase detector polarity, and charge
pump TRI-STATE are defined in the 1.3 FUNCTION AND
INITIALIZATION LATCH section also.
LMX2306/LMX2316/LMX2326
www.national.com
16
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2320 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Frequency Synthesizer for RF Personal Communications |
| LMX2320 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2320TM | 功能描述:IC FREQ SYNTH 2.0GHZ 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2320TMX | 功能描述:IC FREQ SYNTH 2.0GHZ 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2322 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinumTM 2.0 GHz Frequency Synthesizer for RF Personal Communications |
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