參數(shù)資料
型號： LMX2313USLDX/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 600 MHz, QCC20
封裝： LEAD FREE, THIN, CSP-20
文件頁數(shù)： 21/29頁
文件大?。?/td> 662K
代理商： LMX2313USLDX/NOPB
3.0 Programming Description (Continued)
3.3.3 B_CNTR[12:0]
B COUNTER
N[19:7]
The NB_CNTR control word is used to program the B counter. The B counter is a 13-bit binary counter used in the programmable
feedback divider. The B counter can be programmed to values ranging from 3 to 8,191. See Section 1.4 for details on how the
value of the B counter should be selected.
Divider Value
B_CNTR[12:0]
3
0000000000011
4
0000000000101
8,191
1111111111111
NOTE: B counter divide ratio must be
≥ 3.
3.3.4 A_CNTR[4:0]
A Counter
N[6:2]
The NA_CNTR control word is used to program the A counter. The A counter is a 5-bit swallow counter used in the programmable
feedback divider. The A counter can be programmed to values ranging from 0 to 31. See Section 1.4 for details on how the value
of the A counter should be selected.
Divide
Ratio
A_CNTR[4:0]
0
0000
0
1
0000
1
31
1111
1
NOTES: A counter divide ratio must be
≤ P and A counter divide ratio must be ≤ B counter divide ratio.
3.4 T REGISTER
The T register contains the TO_CNTR control word and FoLD2 control bit. The detailed descriptions and programming
information for each control word is discussed in the following sections.
Register
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21
20
19
18
17
16
15
14
13
12
11
10
98765432
1
0
Data Field
Address
Field
T
0000000
FoLD2
TO_CNTR[11:0]
1
0
3.4.1 FoLD2
FoLD Output (P/O Output Truth Table)
T[14]
See Section 3.2.5 for FoLD Output Truth Table details.
3.4.2 TO_CNTR[11:0]
Timeout Counter Table
T[13:2]
When the Fastlock Timeout counter (TO_CNTR) is loaded with 0, Fastlock is off, the FL pin will be in TRI-STATE mode, and the
charge pump current will be the value specified by the Charge Pump Magnitude bit, R[18]. When the Timeout counter is loaded
with 1, the FL pin is 0 (pulled low) and the charge pump current will be at the 4X state. When the Timeout counter is loaded with
2, the FL pin will again be set to 0 (pulled low), but the charge pump current will be controlled by R[18]. When the Timeout counter
is loaded with 3, the FL pin is 1 (pulled high) with the charge pump current will be controlled by R[18]. When loaded with 4 through
4095, Fastlock is active and will time-out after the specified number of phase detector events.
Count
TO_CNTR[11:0]
Notes
FL Pin Forced TRI-STATE
000000000000
C
P current controlled by R[18]
FL Pin Forced Low
000000000001
C
P = 4 mA (manual Fastlock mode)
FL Pin Forced Low
000000000010
C
P current controlled by R[18]
FL Pin Forced High
000000000011
C
P current controlled by R[18]
Min Count (4)
000000000100
C
P Current set to 4 mA, switches to 1 mA
when count reaches 0
Max Count (4095)
111111111111
LMX2310U/LMX231
1U/LMX2312U/LMX2313U
www.national.com
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