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參數(shù)資料
| 型號： | LMX2313USLDX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 600 MHz, QCC20 |
| 封裝： | LEAD FREE, THIN, CSP-20 |
| 文件頁數(shù)： | 18/29頁 |
| 文件大小： | 662K |
| 代理商： | LMX2313USLDX/NOPB |
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2.0 Power-Down
The LMX2310/1/2/3U are power controlled through logical
control of the CE pin in conjunction with programming of the
PDWN and CPo_TRI bits. A truth table is provided that
describes how the state of the CE pin, the PDWN bit and
CPo_TRI bit set the operating mode of the device. A com-
plete programming description of Power-Down is provided in
Section 3.3.1.
CE
PWDN
CPo_TRI
Operating Mode
0
X
Power-down (Asynchronous)
1
0
Normal Operation
1
0
Power-down (Synchronous)
1
Power-down (Asynchronous)
X = Don’t Care
When the device enters the power-down mode, the oscillator
buffer, RF prescaler, phase detector, and charge pump cir-
cuits are all disabled. The OSC
IN, CPo, FIN,FINB, LD pins
are all forced to a high impedance state. The reference
divider and feedback divider circuits are disabled and held at
the load point during power-down. When the device is pro-
grammed to normal operation, the oscillator buffer, RF pres-
caler, phase detector, and charge pump circuits are all pow-
ered on. The feedback divider and the reference divider are
held at the load point. This allows the RF prescaler, feedback
divider, reference oscillator, the reference divider and pres-
caler circuitry to reach proper bias levels. After a 1.5 s
delay, the feedback and reference divider are enabled and
they resume counting in “close” alignment (The maximum
error is one prescaler cycle). The MICROWIRE control reg-
ister remains active and capable of loading and latching in
data while in the power-down mode.
The synchronous power-down function is gated by the
charge pump. When the device is configured for synchro-
nous power-down, the device will enter the power-down
mode upon the completion of the next charge pump pulse
event.
The asynchronous power-down function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous power-down, the part will go
into power-down mode immediately.
3.0 Programming Description
3.1 MICROWIRE INTERFACE
The MICROWIRE interface is comprised of a 22-bit shift register and three control registers. The shift register consists of a 20-bit
DATA field and a 2-bit address (ADDR) field as shown below. Data is loaded into the shift register on the rising edges of the
CLOCK signal MSB first. When Latch Enable transitions HIGH, data stored in the shift register is loaded into either the R, N or
T register depending on the state of the ADDR bit. The DATA field assignments for the R, N and T registers are shown in Section
3.1.1.
MSB
LSB
DATA
ADDRESS
21
2
0
ADDR
Target Register
0
R register
1
N register
2
T register
3.1.1 Register Map
Register
Most Significant Bit
SHIFT REGISTER BIT LOCATION
Least Significant Bit
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
65432
1
0
Data Field
Address
Field
R
FoLD1
FoLD0
CPo_
TRI
CP0_
4x
PD_
POL
R_CNTR[14:0]
0
N
PWDN
P
B_CNTR[12:0]
A_CNTR[4:0]
0
1
T
0
FoLD2
TO_CNTR[11:0]
1
0
LMX2310U/LMX231
1U/LMX2312U/LMX2313U
www.national.com
25
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