參數(shù)資料
型號(hào): LMX2306
廠商: National Semiconductor Corporation
英文描述: PLLatinum Low Power Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個(gè)人通訊的低耗頻率合成器)
中文描述: PLLatinum頻率合成器的低功耗射頻個(gè)人通信(PLLatinum技術(shù)用于射頻個(gè)人通訊的低耗頻率合成器)
文件頁(yè)數(shù): 2/19頁(yè)
文件大?。?/td> 300K
代理商: LMX2306
Connection Diagrams
Pin Descriptions
16-Pin
TSSOP
16-Pin
CSP
15
Pin
Name
FL
o
I/O
Description
1
O
FastLock Output. For connection of parallel resistor to the loop filter. (See Section 1.3.4
FASTLOCK MODES description.)
Charge Pump Output. For connection to a loop filter for driving the input of an external VCO.
Charge Pump Ground.
Analog Ground.
RF Prescaler Complementary Input. A bypass capacitor should be placed as close as possible to
this pin and be connected directly to the ground plane. The complementary input can be left
unbypassed, with some degradation in RF sensitivity.
RF Prescaler Input. Small signal input from the VCO.
Analog Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2
.
Oscillator Input. This input is a CMOS input with a threshold of approximately V
CC
/2 and an
equivalent 100k input resistance. The oscillator input is driven from a reference oscillator.
Digital Ground.
Chip Enable. A LOW on CE powers down the device and will TRI-STATE the charge pump output.
Taking CE HIGH will power up the device depending on the status of the power down bit F2. (See
Section 1.3.1 POWERDOWN OPERATION and Section 1.7.1 DEVICE PROGRAMMING AFTER
FIRST APPLYING V
CC
.)
High Impedance CMOS Clock Input. Data for the various counters is clocked in on the rising edge
into the 21-bit shift register.
Binary Serial Data Input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
Load Enable CMOS Input. When LE goes HIGH, data stored in the shift registers is loaded into one
of the 3 appropriate latches (control bit dependent).
Multiplexed Output of the RF Programmable or Reference Dividers and Lock Detect. CMOS output.
(See Table 4)
Digital Power Supply Voltage Input. Input may range from 2.3V to 5.5V. Bypass capacitors should
be placed as close as possible to this pin and be connected directly to the ground plane. V
CC1
must equal V
CC2
.
Power Supply for Charge Pump. Must be
V
CC
.
2
3
4
5
16
1
2
3
CP
o
GND
GND
f
IN
O
I
6
7
4
5
f
IN
I
V
CC1
8
6
OSC
IN
I
9
7
8
GND
CE
10
I
11
9
Clock
I
12
10
Data
I
13
11
LE
I
14
12
Fo/LD
O
15
13
V
CC2
16
14
V
P
LMX2306/16/26
DS100127-2
16-Lead (0.173” Wide) Thin Shrink Small Outline
Package(TM)
Order Number LMX2306TM, LMX2306TMX,
LMX2316TM, LMX2316TMX,
LMX2326TM or LMX2326TMX
See NS Package Number MTC16
LMX2306/16/26
DS100127-19
16-pin Chip Scale Package
Order Number LMX2306SLBX, LMX2316SLBX or
LM2326SLBX
See NS Package Number SLB16A
L
www.national.com
2
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2306_04 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Frequency Synthesizer for RF Personal Communications
LMX2306LBX 制造商:未知廠家 制造商全稱:未知廠家 功能描述:FREQUENCY SYNTHESIZER|BICMOS|LLCC|16PIN|PLASTIC
LMX2306SLBX 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 25MHz to 550MHz 16-Pin LAM CSP T/R
LMX2306SLBX/NOPB 功能描述:IC FREQ SYNTH 16LAMINATE CSP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器,PLL,頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2306TM 制造商:Texas Instruments 功能描述:PLL Frequency Synthesizer Single 25MHz to 550MHz 16-Pin TSSOP Rail 制造商:Texas Instruments 功能描述:550MHZ SINGLE PLL 2306 TSSOP16