參數(shù)資料
型號： LMK04010BISQE/NOPB
廠商： National Semiconductor
文件頁數(shù)： 4/65頁
文件大小： 0K
描述： IC CLOCK COND 1.2GHZ W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
類型： 時鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS
輸出： 2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:5
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.296GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
其它名稱： LMK04010BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Internal VCO Closed Loop Phase Noise and Jitter Specifications using an Instrumentation Quality VCXO
Offset = 1 kHz
-111
Offset = 10kHz
-119
LMK040x0 (13)
Offset = 100 kHz
-121
fVCO = 1200 MHz
SSB Phase Noise
Offset = 1 MHz
-133
dBc/Hz
PLL2 = Closed Loop
Offset = 10 MHz
-157
Measured at Fout
Offset = 20 MHz
-162
Offset = 40 MHz
-165
Offset = 1 kHz
-110
Offset = 10 kHz
-117
LMK040x1 (14)
Offset = 100 kHz
-120
fVCO = 1500 MHz
SSB Phase Noise
Offset = 1 MHz
-132
dBc/Hz
PLL2 = Closed Loop
Offset = 10 MHz
-156
Measured at Fout
Offset = 20 MHz
-160
Offset = 40 MHz
-163
L(f)Fout
Offset = 1 kHz
-111
Offset = 10 kHz
-118
LMK040x2 (15)
Offset = 100 kHz
-120
fVCO = 1600 MHz
SSB Phase Noise
Offset = 1 MHz
-132
dBc/Hz
PLL2 = Closed Loop
Offset = 10 MHz
-156
Measured at Fout
Offset = 20 MHz
-162
Offset = 40 MHz
-165
Offset = 1 kHz
-107
Offset = 10 kHz
-114
LMK040x3 (16)
Offset = 100 kHz
-117
fVCO = 2000 MHz
SSB Phase Noise
Offset = 1 MHz
-126
dBc/Hz
PLL2 = Closed Loop
Offset = 10 MHz
-152
Measured at Fout
Offset = 20 MHz
-156
Offset = 40 MHz
-160
(13) For LMK040x0, fVCO = 1200 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(14) For LMK040x1, fVCO = 1500 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 3, N2 = 5, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
268 kHz, PM = 75°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(15) For LMK040x2, fVCO = 1600 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 8, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW =
252 kHz, PM = 76°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
(16) For LMK040x3, fVCO = 2000 MHz. PLL1 is powered down. A 100 MHz Wenzel XO (model: 501-04623G) drives the OSCin input of
PLL2. PLL2 parameters: VCO_DIV = 2, N2 = 10, R2 = 1, FDET = 100 MHz, ICP2 = 1.6 mA, C1 = 22 pF, C2 = 5.6 nF, R2 = 1.8 kΩ, LBW
= 434 kHz, PM = 69°. Wenzel XO phase noise: 100 Hz: -132 dBc/Hz; 1 kHz: -147 dBc/Hz; 10 kHz: -159 dBc/Hz; 100 kHz: -167 dBc/Hz.
12
Copyright 2008–2011, Texas Instruments Incorporated
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