參數(shù)資料
型號： LMK04000BISQ/NOPB
廠商： National Semiconductor
文件頁數(shù)： 9/65頁
文件大小： 0K
描述： IC CLOCK CONDITIONER W/PLL 48LLP
標(biāo)準(zhǔn)包裝： 1,000
系列： PowerWise®
類型： 時鐘調(diào)節(jié)器
PLL： 是
輸入： LVCMOS，晶體
輸出： LVCMOS，2VPECL，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 3:7
差分 - 輸入:輸出： 是/是
頻率 - 最大： 1.296GHz
除法器/乘法器： 是/是
電源電壓： 3.15 V ~ 3.45 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-LLP（7x7）
包裝： 帶卷 (TR)
其它名稱： LMK04000BISQ
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LMK040x0 (34)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
230
Integrated RMS Jitter
LMK040x1 (35)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
220
Integrated RMS Jitter
JCLKout
fs
LVCMOS
LMK040x2 (36)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
230
Integrated RMS Jitter
LMK040x3 (37)
BW = 12 kHz to 20 MHz
240
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
260
Integrated RMS Jitter
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH
High-Level Input Voltage
1.6
VCC
V
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
-5
25
A
IIL
Low-Level Input Current
VIL = 0
-5.0
5.0
A
Digital Inputs (GOE, SYNC*)
VIH
High-Level Input Voltage
1.6
VCC
V
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
-5.0
5.0
A
IIL
Low-Level Input Current
VIL = 0
-40.0
5.0
A
Digital Outputs (CLKinX_LOS, LD)
VOH
High-Level Output Voltage
IOH = -500 A
VCC - 0.4
V
VOL
Low-Level Output Voltage
IOL = 500 A
0.4
V
Default Power On Reset Clock Output Frequency
CLKout2, LM040x0
50
CLKout2, LM040x1
62
Default output clock frequency
fCLKout-startup
MHz
at device power on
CLKout2, LM040x2
68
CLKout2, LM040x3
81
LVDS Clock Outputs (CLKoutX)
Maximum Frequency
fCLKout
RL = 100 Ω
1080
MHz
(38)
CLKoutX to CLKoutY
LVDS-LVDS, T = 25 °C,
TSKEW
30
ps
(39)
FCLK = 800 MHz, RL= 100 Ω
VOD
Differential Output Voltage
250
350
450
mV
Change in Magnitude of VOD
R = 100
Ω differential
ΔVOD
for complementary output
-50
50
mV
termination, AC coupled to
states
receiver input,
FCLK = 800 MHz,
VOS
Output Offset Voltage
1.125
1.25
1.375
V
T = 25 °C
Change in VOS for
ΔVOS
35
|mV|
complementary output states
ISA
Output short circuit current -
Single-ended output shorted to
-24
24
mA
ISB
single ended
GND, T = 25 °C
Output short circuit current -
Complimentary outputs tied
ISAB
-12
12
mA
differential
together
LVPECL Clock Outputs (CLKoutX) (40)
(38) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to of a period, or, 0.5/FCLKoutX.
(39) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for
delay mode.
(40) LVPECL/2VPECL is programmable for all NSIDs.
Copyright 2008–2011, Texas Instruments Incorporated
17
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