參數(shù)資料
型號(hào)： LMF100CIWM
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 模擬濾波器
英文描述： High Performance Dual Switched Capacitor Filter
中文描述： DUAL SWITCHED CAPACITOR FILTER, RESISTOR PROGRAMMABLE, UNIVERSAL, PDSO20
封裝： SOP-20
文件頁(yè)數(shù)： 2/28頁(yè)
文件大?。?/td> 868K
代理商： LMF100CIWM
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
(Note 14)
Supply Voltage (V
+
V
)
Voltage at Any Pin
16V
V
+
+ 0.3V
V
0.3V
5 mA
20 mA
500 mW
150C
2000V
Input Current at Any Pin (Note 2)
Package Input Current (Note 2)
Power Dissipation (Note 3)
Storage Temperature
ESD Susceptability (Note 11)
Soldering Information
N Package: 10 sec.
260C
J Package: 10 sec.
SO Package:
Vapor Phase (60 sec.)
Infrared (15 sec.)
See AN-450 “Surface Mounting Methods and Their Effect
on Product Reliability” (Appendix D) for other methods of
soldering surface mount devices.
300C
215C
220C
Operating Ratings
(Note 1)
Temperature Range
LMF100CCN
LMF100CIWM
Supply Voltage
T
MIN
≤
T
A
≤
T
MAX
0C
≤
T
A
≤
+70C
40C
≤
T
A
≤
+85C
4V
≤
V
+
V
≤
15V
Electrical Characteristics
The following specifications apply for Mode 1, Q = 10 (R
= R
= 100k, R
2
= 10k), V
+
= +5V and V
= 5V unless otherwise
specified.
Boldface limits apply for T
MIN
to T
MAX
; all other limits T
A
= T
J
= 25C.
Symbol
Parameter
Conditions
LMF100CCN
Tested
Limit
(Note 9)
13
LMF100CIWM
Tested
Limit
(Note 9)
13
Units
Typical
(Note 8)
Design
Limit
(Note 10)
13
Typical
(Note 8)
Design
Limit
(Note 10)
I
s
Maximum Supply Current
f
CLK
= 250 kHz
No Input Signal
9
9
mA
f
0
Center Frequency
Range
Clock Frequency
Range
Clock to Center Frequency
Ratio Deviation
Q Error (MAX) (Note 4)
MIN
MAX
MIN
MAX
0.1
100
5.0
3.5
±
0.2
0.1
100
5.0
3.5
±
0.2
Hz
kHz
Hz
MHz
%
f
CLK
f
CLK
/f
0
V
Pin12
= 5V or 0V
f
CLK
= 1 MHz
Q = 10, Mode 1
V
Pin12
= 5V or 0V
f
CLK
= 1 MHz
±
0.8
±
0.8
±
0.8
±
0.5
±
5
±
6
±
0.5
±
6
%
H
OBP
H
OLP
Bandpass Gain at f
0
DC Lowpass Gain
f
CLK
= 1 MHz
R
1
= R
2
= 10k
f
CLK
= 250 kHz
f
CLK
= 250 kHz
f
CLK
= 250 kHz
0
0
±
0.4
±
0.2
±
0.4
±
0.2
0
0
±
0.4
±
0.2
dB
dB
V
OS1
V
OS2
DC Offset Voltage (Note 5)
DC Offset Voltage (Note 5)
±
5.0
±
30
±
15
±
15
±
15
±
80
±
70
±
40
±
15
±
80
±
70
±
60
±
5.0
±
30
±
15
±
15
±
15
±
80
±
70
±
60
mV
mV
mV
mV
S
A/B
= V
+
S
A/B
= V
V
OS3
DC Offset Voltage (Note 5)
Crosstalk (Note 6)
f
CLK
= 250 kHz
A Side to B Side or
B Side to A Side
f
CLK
= 250 kHz
20 kHz Bandwidth
100:1 Mode
f
CLK
= 250 kHz 100:1 Mode
60
60
dB
Output Noise (Note 12)
N
BP
LP
40
320
300
6
40
320
300
6
μV
Clock Feedthrough
(Note 13)
Minimum Output
Voltage Swing
mV
V
OUT
R
L
= 5k
(All Outputs)
R
L
= 3.5k
(All Outputs)
+4.0
4.7
+3.9
4.6
5
20
12
±
3.8
±
3.7
+4.0
4.7
+3.9
4.6
5
20
12
±
3.7
V
V
GBW
SR
I
sc
Op Amp Gain BW Product
Op Amp Slew Rate
Maximum Output
Short
Circuit Current
(Note 7)
MHz
V/μs
mA
Source
(All Outputs)
Sink
45
45
mA
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