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參數(shù)資料
| 型號(hào)： | LMD18400N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Quad High Side Driver |
| 中文描述： | 3.75 A BUF OR INV BASED PRPHL DRVR, PDIP20 |
| 封裝： | N20A |
| 文件頁(yè)數(shù)： | 7/18頁(yè) |
| 文件大?。?/td> | 329K |
| 代理商： | LMD18400N |
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Applications Information
BASIC OPERATION
High-side drivers are used extensively in automotive and
industrial applications to switch power to ground referred
loads. The major advantage of using high-side drive, as op-
posed to low-side drive, is to protect the load from being
energized in the event that the load drive wire is inadver-
tently shorted to ground as shown in Figure 1. A high-side
driver can sense a shorted condition and open the power
switch to disable the load and eliminate the excessive cur-
rent drain on the power supply. The LMD18400 can control
and protect up to four separate ground referenced loads.
High Side Drive
TL/H/11026–9
Low Side Drive
TL/H/11026–10
FIGURE 1. High-Side vs Low-Side Drive
The LMD18400 combines low voltage CMOS logic control
circuitry with a high voltage DMOS process. Each DMOS
power switch has an individual ON/OFF control input. When
commanded ON, the output of the switch will connect the
load to the V
CC
supply through a maximum resistance of
1.3
X
(the ON resistance of the DMOS switch). The voltage
applied to the load will depend upon the load current and
the designed current capability of the LMD18400. When a
switch is commanded OFF, the load will be disconnected
from the supply except for a small leakage current of typi-
cally less than 0.01
m
A.
The LMD18400 can be continually connected to a live pow-
er source, a car battery for example, while drawing less than
10
m
A from the power source when put into a ‘‘sleep’’ con-
dition. This ‘‘sleep’’ mode is enacted by taking the Enable
Input (pin 3) low. During this mode the supply current for the
device is typically only 0.04
m
A. Special low current con-
sumption standby circuitry is used to hold the DMOS
switches OFF to eliminate the possibility of supply voltage
transients from turning on any of the loads (a common prob-
lem with MOS power devices). When in the ‘‘sleep’’ mode,
all diagnostic and logic circuitry is inactive. When the Enable
Input is taken to a logic 1, the switches become ‘‘a(chǎn)rmed’’
and ready to respond to their control input after a short,
30
m
s, enable delay time. This delay interval prevents the
switches from transient turn-on. Figure 2 shows the switch
control logic.
TL/H/11026–11
FIGURE 2. Control Logic for Each Power Switch
Each DMOS switch is turned ON when its gate is driven
approximately 3.5V more positive than its source voltage.
Because the source of the switch is the output terminal to
the load it can be taken to a voltage very near the V
CC
supply potential. To ensure that there is sufficient voltage
available to drive the gates of the DMOS device a charge
pump circuit is built in. This circuit is controlled by an internal
300 kHz oscillator and using an external 10 nF capacitor
connected from pin 14 to ground generates a voltage that is
approximately 20V greater than the V
CC
supply voltage.
This provides sufficient gate voltage drive for each of the
switches which is applied under command of standard 5V
logic input levels.
The turn-on time for each switch is approximately 12
m
s
when driving a 1A load current. This relatively slow switch-
ing time is beneficial in minimizing electromagnetic interfer-
ence (EMI) related problems created from switching high
current levels.
http://www.national.com
7
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