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參數(shù)資料
| 型號： | LMC567CN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 信令電路 |
| 英文描述： | Low Power Tone Decoder |
| 中文描述： | TELECOM, TONE DECODER CIRCUIT, PDIP8 |
| 封裝： | PLASTIC, DIP-8 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 168K |
| 代理商： | LMC567CN |
Applications Information
(refer to Block
Diagram) (Continued)
SUPPLY DECOUPLING
The decoupling of supply pin 4 becomes more critical at high
supply voltages with high operating frequencies, requiring
C4 to be placed as close as possible to pin 4.
INPUT PIN
The input pin 3 is internally ground-referenced with a nomi-
nal 40 k
resistor. Signals which are already centered on 0V
may be directly coupled to pin 3; however, any d.c. potential
must be isolated via a coupling capacitor. Inputs of multiple
LMC567 devices can be paralleled without individual d.c.
isolation.
LOOP FILTER
Pin 2 is the combined output of the phase detector and con-
trol input of the VCO for the phase-locked loop (PLL). Ca-
pacitor C2 in conjunction with the nominal 80 k
pin 2 inter-
nal resistance forms the loop filter.
For small values of C2, the PLL will have a fast acquisition
time and the pull-in range will be set by the built in VCO fre-
quency stops, which also determine the largest detection
bandwidth (LDBW). Increasing C2 results in improved noise
immunity at the expense of acquisition time, and the pull-in
range will begin to become narrower than the LDBW (see
Bandwidth as a Function of C2 curve). However, the maxi-
mum hold-in range will always equal the LDBW.
OUTPUT FILTER
Pin 1 is the output of a negative-going amplitude detector
which has a nominal 0 signal output of 7/9 V
. When the PLL
is locked to the input, an increase in signal level causes the
detector output to move negative. When pin 1 reaches
2/3 V
s
the output is activated (see OUTPUT PIN).
Capacitor C1 in conjunction with the nominal 40 k
pin 1 in-
ternal resistance forms the output filter. The size of C1 is a
tradeoff between slew rate and carrier ripple at the output
comparator. Low values of C1 produce the least delay be-
tween the input and output for tone burst applications, while
larger values of C1 improve noise immunity.
Pin 1 also provides a means for shifting the input threshold
higher or lower by connecting an external resistor to supply
or ground. However, reducing the threshold using this tech-
nique increases sensitivity to pin 1 carrier ripple and also re-
sults in more part to part threshold variation.
OUTPUT PIN
The output at pin 8 is an N-channel FET switch to ground
which is activated when the PLL is locked and the input tone
is of sufficient amplitude to cause pin 1 to fall below 2/3 V
s
.
Apart from the obvious current component due to the exter-
nal pin 8 load resistor, no additional supply current is re-
quired to activate the switch. The on resistance of the switch
is inversely proportional to supply; thus the “sat” voltage for
a given output current will increase at lower supplies.
www.national.com
5
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMC567CN NOPB | 制造商:National Semiconductor 功能描述:Tone Decoder 8-Pin PDIP T/R |
| LMC567CN | 制造商:Texas Instruments 功能描述:IC TONE DECODER CMOS DIP8 567 |
| LMC567CN/NOPB | 功能描述:電話振鈴器 Low Power Tone Decoder RoHS:否 制造商:NJR 產(chǎn)品:FSK Demodulator / Tone Decoder 封裝 / 箱體:DIP-14 頻率:0.01 Hz to 300 KHz 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
| LMC568 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Power Phase-Locked Loop |
| LMC568CM | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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