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參數(shù)資料
| 型號： | LM98725 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁數(shù)： | 4/14頁 |
| 文件大小： | 464K |
| 代理商： | LM98725 |
Symbol
Parameter
Conditions
Min
(Note
9)
Typ
Max
Units
f
SCLK
Input Clock Frequency
f
SCLK <= fINCLK
27/30/30
MHz
INCLK = PIXCLK
(Pixel Rate Clock)
Mode 3/2/1
f
SCLK <= fINCLK
81/60/30
MHz
INCLK = ADCCLK
(ADC Rate Clock)
Mode 3/2/1
SCLK Duty Cycle
50/50
ns
t
IH
Input Hold Time
1.5
ns
t
IS
Input Setup Time
2.5
ns
t
SENSC
SCLK Start Time After SEN Low
1.5
ns
t
SCSEN
SEN High after last SCLK Rising
Edge
2.5
ns
t
SENW
SEN Pulse Width
INCLK present
6
T
INCLK
INCLK stopped
50
ns
t
OD
Output Delay Time
11
14
ns
t
HZ
Data Output to High Z
0.5
T
SCLK
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions. Operation of the device beyond the Operating Ratings is not recommended.
Note 2:
All voltages are measured with respect to AGND = DGND = 0V, unless otherwise specified.
Note 3:
When the input voltage (V
IN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25
mA to two.
Note 4:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
JMAX, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is P
D = (TJMAX – TA)/θJA. The values for maximum power dissipation listed above will be reached only when the
device is operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).
Such conditions should always be avoided.
Note 5:
Human body model is 100 pF capacitor discharged through a 1.5 k
resistor. Machine model is 220 pF discharged through 0.
Note 6:
Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 7:
The analog inputs are protected as shown below. Input voltage magnitudes beyond the supply rails will not damage the device, provided the current is
limited per note 3. However, input errors will be generated If the input goes above VA and below AGND.
30085371
Note 8:
Typical figures are at T
A = 25°C, and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 9:
Test limis are guaranteed to National's AOQL (Average Outgoing Quality Level).
Note 10:
This parameter guaranteed by design and characterization.
Note 11:
If the input INCLK is divided down to a lower internal clock rate via the PLL, the parameter t
SENW will be increased by the same factor.
Note 12:
When the Spread Spectrum Clock Generation feature is enabled, t
SENW should be increased by 1.
www.national.com
12
LM98725
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