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參數(shù)資料
| 型號(hào)： | LM98503CCVV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 18 MSPS Camera Signal Processor |
| 中文描述： | 10位，18 MSPS的攝像機(jī)信號(hào)處理器 |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 203K |
| 代理商： | LM98503CCVV |
www.national.com
24
Applications Information
(continued)
Figure 17: Recommended Layout Pattern
LM98503
Analog Ground Plane
Digital Ground Plane
C
C
C
C
C
R
C
Narrow, single point connection between
analog and digital ground planes
Short clock trace does not cross other
signal traces.
Bypass capacitors located close to
reference pins.
All analog circuitry mounted atop analog
ground plane and all digital circuitry mounted
atop digital ground plane.
8.0 Dynamic Performance
The LM98503 is AC tested and its dynamic performance is
guaranteed. The clock source driving the CLK input must be free
of jitter. For best AC performance, the clock source should be
isolated from other system digital circuitry with a clock tree
buffer(s). Meeting noise specifications depends largely upon
keeping digital noise out of the analog input of the LM98503.
9.0 Common Application Pitfalls
Driving the inputs (analog or digital) beyond the power
supply potential.
For proper operation, all input potentials
should not be greater than 300mV above that of the power
supply. It is not uncommon for high speed digital circuits (e.g.
74F and 74AC devices) to exhibit undershoot that falls to a
potential greater than 1.0 Volt below the ground potential and
overshoot that rises to a potential greater than 1.0 Volt above
the power supply potential. A resistor of 50
to 100
in series
with the offending digital input will, in most cases, eliminate this
problem.
Attempting to drive a high capacitance digital data bus.
The
more capacitance the output drivers have to charge for each
conversion output, the more current is required from the DV+ I/O
and DGND I/O supply pins. The large charging current spikes
can couple into the analog section and subsequently may
degrade dynamic performance of the system. Adequate
bypassing and maintaining separate analog and digital ground
planes will reduce this problem on the application system board.
Buffering the digital data outputs may be necessary if the data
bus being driven by the LM98503 is heavily loaded. Dynamic
performance may also be improved by adding series resistors of
47
at each digital output.
Driving the reference pins with devices that cannot source
or sink the current required by the reference resistor ladder.
As mentioned previously, any devices driving the reference
resistor ladder must source sufficient current into the top of the
ladder. Additionally, the device connected to the bottom ofladder
voltages are not stable the converter output will not generate
ladder must be able to sink the necessary amount of current to
thekeep the reference voltage(s) stable. If the reference resistor
predictable output codes.
L
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