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參數(shù)資料
| 型號： | LM98503CCVV |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 10-Bit, 18 MSPS Camera Signal Processor |
| 中文描述： | 10位，18 MSPS的攝像機(jī)信號處理器 |
| 文件頁數(shù)： | 11/25頁 |
| 文件大?。?/td> | 203K |
| 代理商： | LM98503CCVV |
www.national.com
11
CDS Sampling Timing
Figure 4: Pixel Rate Reset Voltage Sampling
Figure 5: Pixel Rate Video Signal Sampling
CCD
SHP
1
CLAMP
2
CLK
1
SHP overrides the CLAMP signal’s falling edge for sampling the reset voltage (SHP is active-low by default).
2
The CLAMP signal is an internal signal derived from the CLK input whose falling edge samples the CCD reset voltage by default.
t
AD
t
SHP
CCD
SHD
1
CLK
1
SHD overrides the SAMPLE signal’s falling edge for sampling the video signal (SHD is active-low by default).
2
The SAMPLE signal is an internal signal derived from the CLK input whose falling edge samples the CCD video signal by default.
t
AD
t
SHD
SAMPLE
2
L
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