參數(shù)資料
型號: LM73
廠商: National Semiconductor Corporation
元件分類: 溫度/濕度傳感器
英文描述: 2.7V, SOT-23, 11-to-14 Bit Digital Temperature Sensor with 2-Wire Interface
中文描述: 為2.7V,采用SOT - 23,11至14位數(shù)字溫度傳感器,2線接口
文件頁數(shù): 5/18頁
文件大?。?/td> 732K
代理商: LM73
Logic Electrical Characteristics
DIGITAL DC CHARACTERISTICS
Unless otherwise noted, these specifications apply for V
= 2.7V to 5.5V.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= +25C, unless otherwise noted. T
A
is the ambient temperature. T
J
is the junction temperature.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
Units
(Limit)
SMBDAT, SMBCLK INPUTS
V
IH
V
IL
V
IN;HYST
Logical “1” Input Voltage
Logical “0” Input Voltage
SMBDAT and SMBCLK Digital Input
Hysteresis
Logical “1” Input Current
Logical “0” Input Current
Input Capacitance
SMBDAT, ALERT OUTPUTS
I
OH
High Level Output Current
V
OL
SMBus Low Level Output Voltage
ADDRESS INPUT
V
IH;ADDRESS
Address Pin High Input Voltage
V
IL;ADDRESS
Address Pin Low Input Voltage
I
IH; ADDRESS
Address Pin High Input Current
I
IL;ADDRESS
Address Pin Low Input Current
SMBus DIGITAL SWITCHING CHARACTERISTICS
0.7*V
DD
0.3*V
DD
V (min)
V (max)
V
0.07*V
DD
I
IH
I
IL
C
IN
V
IN
= V
DD
V
IN
= 0 V
0.01
–0.01
5
2
μA (max)
μA (max)
pF
–2
V
OH
= V
DD
I
OL
= 3 mA
0.01
2
μA (max)
V (max)
0.4
V
DD
minus 0.100
0.100
2
–2
V (min)
V (max)
μA (max)
μA (max)
V
IN
= V
DD
V
IN
= 0 V
0.01
–0.01
Unless otherwise noted, these specifications apply for V
= +2.7 V to +5.5 V, C
(load capacitance) on output lines = 400 pF.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
;
all other limits T
A
= T
J
= +25C, unless otherwise noted.
Symbol
Parameter
Conditions
Typical
(Note 6)
Limits
(Note 7)
400
100
300
300
250
Units
(Limit)
kHz (max)
Hz (min)
ns (min)
ns (min)
ns (max)
f
SMB
SMBus Clock Frequency
t
LOW
t
HIGH
t
F;SMBO
SMBus Clock Low Time
SMBus Clock High Time
Output Fall Time (Note 10)
C
L
= 400 pF
I
PULL-UP
3 mA
t
TIMEOUT
SMBDAT and SMBCLK Time Low for Reset of
Serial Interface (Note 11)
t
SU;DAT
Data In Setup Time to SMBCLK High
t
HD;DATI
Data Hold Time: Data In Stable after SMBCLK
Low
t
HD;DATO
Data Hold Time: Data Out Stable after
SMBCLK Low
t
HD;STA
Start Condition SMBDAT Low to SMBCLK
Low (Start condition hold before the first clock
falling edge)
t
SU;STO
Stop Condition SMBCLK High to SMBDAT
Low (Stop Condition Setup)
t
SU;STA
SMBus Repeated Start-Condition Setup Time,
SMBCLK High to SMBDAT Low
t
BUF
SMBus Free Time Between Stop and Start
Conditions
t
POR
Power-On Reset Time (Note 12)
15
45
100
0
ms (min)
ms (max)
ns (min)
ns (min)
30
ns (min)
60
ns (min)
50
ns (min)
50
ns (min)
1.2
μs (min)
1
ms (max)
L
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