參數(shù)資料
型號(hào): LM64CILQ-F
廠商: National Semiconductor Corporation
英文描述: UART W/16BYTE TX/RX FIFO
中文描述: 【1ΣC遠(yuǎn)程二極管溫度傳感器,PWM風(fēng)扇控制和5個(gè)GPIO的
文件頁數(shù): 17/29頁
文件大?。?/td> 376K
代理商: LM64CILQ-F
2.0 LM64 Registers
(Continued)
Register
[HEX]
CONVERSION AND ONE-SHOT REGISTERS
04 (0A)
Conversion Rate
0F
One-Shot
ALERT STATUS AND MASK REGISTERS
02
ALERT Status
16
ALERT Mask
ID REGISTERS
FE
Manufacturer’s ID
FF
Stepping/Die Rev. ID
GENERAL PURPOSE REGISTERS
1A
General Purpose Input
1B
General Purpose Output
[RESERVED] REGISTERS—NOT USED
06
Not Used
0C
Not Used
15
Not Used
17
Not Used
18
Not Used
1C–1F
Not Used
20
Not Used
22–2F
Not Used
30–3F
Not Used
40–45
Not Used
4E
Not Used
60–BE
Not Used
C0–FD
Not Used
Register Name
Read/Write
POR Default
[HEX]
R/W
08
N/A
Write Only
Read Only
R/W
N/A
A4
Read Only
Read Only
01
51
Read Only
R/W
(Note 15)
(Note 16)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Note 15:
For Register 0x1A the Power-On-Reset for the five LSB’s are the logic states present on the 5 GPIOx pins.
Note 16:
For Register 0x1B the Power-On-Reset for the five LSB’s are the logic states present on the 5 GPDx pins.
2.3 LM64 INITIAL REGISTER SEQUENCE AND REGISTER DESCRIPTIONS IN FUNCTIONAL ORDER
The following is a Register Map grouped in functional and sequence order. Some address locations have been left blank to
maintain compatibility with LM86. Addresses in parenthesis are mirrors of named address for backwards compatibility with some
older software. Reading or writing either address will access the same 8-bit register.
2.3.1 LM64 Required Initial Fan Control Register Sequence
Important!
The BIOS must follow the sequence below to configure the following Fan Registers for the LM64 before using any of
the Fan or Tachometer or PWM registers:
Step
1
[Register]
HEX
and Setup Instructions
[4A] Write bits 0 and 1; 3 and 4. This includes tach settings if used, PWM internal clock select (1.4 kHz or
360 kHz) and PWM Output Polarity.
[4B] Write bits 0 through 5 to program the spin-up settings.
[4D] Write bits 0 through 4 to set the frequency settings. This works with the PWM internal clock select.
Choose, then write,
only one
of the following:
A. [4F–5F] the Lookup Table,
or
B. [4C] the PWM value bits 0 through 5.
If Step 4A, Lookup Table, was chosen and written then write [4A] bit 5 = 0.
All other registers can be written at any time after the above sequence.
2
3
4
5
L
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