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參數(shù)資料
| 型號(hào)： | LM5115SDX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Secondary Side Post Regulator Controller |
| 中文描述： | 2.5 A SWITCHING CONTROLLER, PDSO16 |
| 封裝： | LLP-16 |
| 文件頁數(shù)： | 10/17頁 |
| 文件大?。?/td> | 725K |
| 代理商： | LM5115SDX |
Synchronization (SYNC) and
Feed-forward (RAMP)
(Continued)
lation is improved because the PWM duty cycle of the aux-
iliary converter is immediately corrected, independent of the
delays of the voltage regulation loop.
The recommended SYNC input current range is 50μA to
150μA. The SYNC pin resistor (R
) should be selected to
set the SYNC current (I
) to 150μA with the maximum
phase signal amplitude, V
. This will guarantee
that I
stays within the recommended range over a 3:1
change in phase signal amplitude. The SYNC pin resistor is
therefore:
R
SYNC
= (V
PHASE(max)
/ 150μA) - 2.5k
Once I
has been established by selecting R
, the
RAMP signal amplitude may be programmed by selecting
the proper RAMP pin capacitor value. The recommended
peak amplitude of the RAMP waveform is 1V to 1.75V. The
C
capacitor is chosen to provide the desired RAMP
amplitude with the nominal phase signal voltage and pulse
width.
C
RAMP
= (3 x I
SYNC
x T
ON
) / V
RAMP
Where
C
RAMP
= RAMP pin capacitance
I
SYNC
= SYNC pin current current
T
ON
= corresponding phase signal pulse width
V
RAMP
= desired RAMP amplitude (1V to 1.75V)
For example,
Main channel output = 3.3V. Phase signal maximum ampli-
tude = 12V. Phase signal frequency = 250kHz
Set I
= 150μA with phase signal at maximum ampli-
tude (12V):
I
SYNC
= 150μA = V
PHASE(max)
/ (R
SYNC
+ 2.5 k
) = 12V /
(R
SYNC
+ 2.5 k
)
R
SYNC
= 12V/150μA - 2.5k
= 77.5k
T
= Main channel duty cycle / Phase frequency =
(3.3V/12V) / 250kHz = 1.1μs
Assume desired V
RAMP
= 1.5V
C
= (3 x I
SYNC
x T
ON
) / V
RAMP
= (3 x 150μAx 1.1μs)
/ 1.5V
C
RAMP
= 330pF
Error Amplifier and Soft-Start (FB,
CO, & COMP, SS)
An internal wide bandwidth error amplifier is provided within
the LM5115 for voltage feedback to the PWM controller. The
amplifier’s inverting input is connected to the FB pin. The
output of the auxiliary converter is regulated by connecting a
voltage setting resistor divider between the output and the
FB pin. Loop compensation networks are connected be-
tween the FB pin and the error amplifier output (COMP). The
amplifier’s non-inverting input is internally connected to the
SS pin. The SS pin is biased at 0.75V by a resistor divider
connected to the internal 1.27V bandgap reference. When
the VCC voltage is below the UVLO threshold, the SS pin is
discharged to ground. When VCC rises and exceeds the
positive going UVLO threshold (4.25V), the SS pin is re-
leased and allowed to rise. If an external capacitor is con-
nected to the SS pin, it will be charged by the internal resistor
divider to gradually increase the non-inverting input of the
error amplifier to 0.75V. The equivalent impedance of the SS
resistor divider is nominally 60k
which determines the
charging time constant of the SS capacitor. During start-up,
the output of the LM5115 converter will follow the exponen-
tial equation:
VOUT(t) = VOUT(final) x (1 - exp(-t/R
SS
x C
SS
))
Where
Rss = internal resistance of SS pin (60k
)
Css = external Soft-Start capacitor
VOUT(final) = regulator output set point
The initial
v /
t of the output voltage is VOUT(final) / Rss x
Css and VOUT will be within 1% of the final regulation level
after 4.6 time constants or when t = 4.6 x Rss x Css.
Pull-up current for the error amplifier output is provided by an
internal 300μA current source. The PWM threshold signal at
the COMP pin can be controlled by either the open drain
error amplifier or the open drain current amplifier connected
through the CO pin to COMP. Since the internal error ampli-
20134913
FIGURE 3. Line Feed-forward Waveforms
L
www.national.com
10
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