參數(shù)資料
型號(hào): LM5102MM
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 外設(shè)及接口
英文描述: High Voltage Half-Bridge Gate Driver with Programmable Delay
中文描述: 1.8 A HALF BRIDGE BASED PRPHL DRVR, PDSO10
封裝: MSOP-10
文件頁數(shù): 8/13頁
文件大小: 368K
代理商: LM5102MM
LM5102 Waveforms
Operational Notes
The LM5102 offers a unique flexibility with independently
programmable delay of the rising edge for both high and low
side driver outputs independently. The delays are set with
resistors at the RT1 and RT2 pins, and can be adjusted from
100 ns to 600 ns. This feature reduces component count,
board space and cost compared to discrete solutions for
adjusting driver dead time. The wide delay programming
range provides the flexibility to optimize drive signal timing
for a wide range of MOSFETs and applications.
The RT pins are biased at 3V and current limited to 1 mA
maximum programming current. The time delay generator
will accommodate resistor values from 5k to 100k with
turn-on delay times that are proportional to the RT resis-
tance. In addition, each RT pin is monitored by a comparator
that will bypass the turn-on delay if the RT pin is pulled below
the timer elimination threshold (1.8V typical). Grounding the
RT pins programs the LM5102 to drive both outputs with
minimum turn-on delay.
STARTUP AND UVLO
Both top and bottom drivers include under-voltage lockout
(UVLO) protection circuitry which monitors the supply volt-
age (V
DD
) and bootstrap capacitor voltage (V
HB
– V
HS
)
independently. The UVLO circuit inhibits each driver until
sufficient supply voltage is available to turn-on the external
MOSFETs, and the built-in hysteresis prevents chattering
during supply voltage transitions. When the supply voltage is
applied to V
DD
pin of LM5102, the top and bottom gates are
20088903
(a)
20088904
(b)
FIGURE 3. Application Timing Waveforms
L
www.national.com
8
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