參數(shù)資料
型號: LM5035AMH-1
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 2000 kHz SWITCHING FREQ-MAX, PDSO28
封裝: TSSOP-28
文件頁數(shù): 19/30頁
文件大?。?/td> 585K
代理商: LM5035AMH-1
Printed Circuit Board Layout
The LM5035A Current Sense and PWM comparators are very
fast, and respond to short duration noise pulses. The compo-
nents at the CS, COMP, SS, OVP, UVLO, DLY and the RT
pins should be as physically close as possible to the IC, there-
by minimizing noise pickup on the PC board tracks.
Layout considerations are critical for the current sense filter.
If a current sense transformer is used, both leads of the trans-
former secondary should be routed to the sense filter com-
ponents and to the IC pins. The ground side of the transformer
should be connected via a dedicated PC board track to the
AGND pin, rather than through the ground plane.
If the current sense circuit employs a sense resistor in the
drive transistor source, low inductance resistors should be
used. In this case, all the noise sensitive, low-current ground
tracks should be connected in common near the IC, and then
a single connection made to the power ground (sense resistor
ground point).
The gate drive outputs of the LM5035A should have short,
direct paths to the power MOSFETs in order to minimize in-
ductance in the PC board traces. The SR control outputs
should also have minimum routing distance through the pulse
transformers and through the secondary gate drivers to the
sync FETs.
The two ground pins (AGND, PGND) must be connected to-
gether with a short, direct connection, to avoid jitter due to
relative ground bounce.
If the internal dissipation of the LM5035A produces high junc-
tion temperatures during normal operation, the use of multiple
vias under the IC to a ground plane can help conduct heat
away from the IC. Judicious positioning of the PC board within
the end product, along with use of any available air flow
(forced or natural convection) will help reduce the junction
temperatures. If using forced air cooling, avoid placing the
LM5035A in the airflow shadow of tall components, such as
input capacitors.
Application Circuit Example
The following schematic shows an example of a 100W half-
bridge power converter controlled by the LM5035A. The op-
erating input voltage range (V
PWR) is 36V to 75V, and the
output voltage is 3.3V. The output current capability is 30
Amps. Current sense transformer T2 provides information to
the CS pin for current limit protection. The error amplifier and
reference, U3 and U5 respectively, provide voltage feedback
via opto-coupler U4. Synchronous rectifiers Q4, Q5, Q6 and
Q7 minimize rectification losses in the secondary. An auxiliary
winding on transformer T1 provides power to the LM5035A
VCC pin when the output is in regulation. The input voltage
UVLO thresholds are
34V for increasing V
PWR, and 32V
for decreasing V
PWR. The circuit can be shut down by driving
the ON/OFF input (J2) below 1.25V with an open-collector or
open-drain circuit. An external synchronizing frequency can
be applied through a 100pF capacitor to the RT input (U1 pin
5). The regulator output is current limited at
34A.
TABLE 2. Differences between LM5035, LM5035A, LM5035A-1, LM5035B, and
LM5035C
Performance Feature:
LM5035
LM5035A
LM5035A-1
LM5035B
LM5035C
Sync Rectifier Dead-time Ratio
(T1:T2)
2:1
3:1
Soft-start: Hiccup Mode Charging
Current
50A:1A
100A:1A
Bootstrap (HB-HS) Under-Voltage
Lockout
5V
3.9V
Start-up Regulator Current
20mA (min)
25mA (min)
40mA (min)
SR State in UVLO Shutdown and
Hiccup Current Limit
High
Low
HO,LO On-Time at Max Duty Cycle 0.5*T-T1–70 ns
0.5*T-T1–70 ns
0.5*T-T1
Soft-Stop after
UVLO
HO,LO
Yes
No
SR1,2
Yes
No
SR1, SR2 VOH (high state output)
VCC
REF (5V)
Package
TSSOP20–EP
LLP24
TSSOP20–EP
LLP24
TSSOP28–EP
TSSOP–20EP
LLP24
TSSOP20–EP
LLP24
T1 = Delay from SR1, SR2 to leading edge of HO, LO
T
= Period of HO or LO
www.national.com
26
LM5035A/LM5035A-1
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