參數(shù)資料
型號: LM4935
廠商: National Semiconductor Corporation
元件分類: ADC
英文描述: Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
中文描述: 音頻子系統(tǒng)的雙模單聲道立體聲耳機和揚聲器放大器的高效率和多功能模數(shù)轉(zhuǎn)換器
文件頁數(shù): 26/112頁
文件大?。?/td> 5017K
代理商: LM4935
12.0 Status & Control Registers
(Continued)
12.6 PLL N DIVIDER CONFIGURATION REGISTER
This register is used to control the feedback divider of the PLL.
TABLE 7. PLL_N (0x03h)
Bits
7:0
Field
PLL_N
Description
Programs the PLL feedback divider as follows:
PLL_N
0 to 10
11
12
13
14
249
250 to 255
Feedback Divider Value
10
11
12
13
14
249
250
The N divider should be set such that the output of the divider is between 0.5 MHz and 5 MHz. (Fin/M)*N will be the target resting
VCO frequency, F
. The N divider should be set such that 40 MHz
<
(Fin/M)*N
<
60 MHz. Fin/M is often referred to as F
comp
(comparison frequency) or F
ref
(reference frequency), in this document F
comp
is used.
The integer division of the N divider is derived from PLL_N such that:
For 9
<
PLL_N
<
251: N = PLL_N
Note 12:
See
Further Notes on PLL Programming
for further details.
L
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