參數(shù)資料
型號(hào)： LM4935
廠商： National Semiconductor Corporation
元件分類： ADC
英文描述： Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
中文描述： 音頻子系統(tǒng)的雙模單聲道立體聲耳機(jī)和揚(yáng)聲器放大器的高效率和多功能模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 16/112頁
文件大?。?/td> 5017K
代理商： LM4935
11.0 System Control
Method 1. I
2
C Compatible Interface
11.1 I
2
C SIGNALS
In I
2
C mode the LM4935 pin SCL is used for the I
2
C clock SCL and the pin SDA is used for the I
2
C data signal SDA. Both these
signals need a pull-up resistor according to I
2
C specification. The I
2
C slave address for LM4935 is
0011010
2
.
11.2 I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when SCL is LOW.
201341Q1
I
2
C Signals: Data Validity
11.3 I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH
while SCL is HIGH. The I
2
C master always generates START and STOP bits. The I
2
C bus is considered to be busy after START
condition and free after STOP condition. During data transmission, I
2
C master can generate repeated START conditions. First
START and repeated START conditions are equivalent, function-wise.
201341Q2
11.4 TRANSFERRING DATA
Every byte put on the SDAline must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data
has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter
releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9
th
clock
pulse, signifying an acknowledge.Areceiver which has been addressed must generate an acknowledge after each byte has been
received.
After the START condition, the I
2
C master sends a chip address. This address is seven bits long followed by an eighth bit which
is a data direction bit (R/W). The LM4935 address is
0011010
2
. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected
register.
201341Q3
I
2
C Chip Address
Register changes take an effect at the SCL rising edge during the last ACK from slave.
L
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相關(guān)PDF資料
PDF描述
LM4935WL Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
LM4935WLX Audio Sub-System with Dual-Mode Stereo Headphone and Mono High Efficiency Loudspeaker Amplifiers and Multi-Purpose ADC
LM4936 Stereo 2W Audio Power Amplifiers with Volume Control and Selectable Control Interface (SPI or I2C)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM49350 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High Performance Audio Codec Sub-System with a Ground-Referenced Stereo Headphone Amplifier
LM49350RL 制造商:Texas Instruments 功能描述:Audio Codec 1ADC / 1DAC 36-Pin uSMD T/R 制造商:Texas Instruments 功能描述:AUDIO CODEC SUBSYSTEM 36MICRO SMDXT
LM49350RL/NOPB 功能描述:接口—CODEC Hi Perf Audio Codec Subsystem RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
LM49350RL/NOPB 制造商:Texas Instruments 功能描述:Audio Codec IC
LM49350RLEVAL 功能描述:音頻 IC 開發(fā)工具 LM49350RL EVAL BOARD RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V
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