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參數(shù)資料
| 型號： | LM4549 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | Codec |
| 英文描述： | AC ’97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound |
| 中文描述： | 交流\u0026#39;97活2.1編解碼器的采樣率轉(zhuǎn)換和國家3D聲音 |
| 文件頁數(shù)： | 15/18頁 |
| 文件大?。?/td> | 324K |
| 代理商： | LM4549 |
Application Information
(Continued)
Register Descriptions
Reset Register (00h)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If a read is performed on this register, the LM4549 will
return a value of 0D50h indicating that National 3D Sound is
implemented, 18bit data is supported for both the ADC’s and
DAC’s, and the volume control for True Line Level Out is
supported.
Master Volume Registers (02h, 04h, 06h)
These registers allow the output levels from LINE_OUT, LN-
LVL_OUT and MONO_OUT to be attenuated or muted.
There are 6-bits of volume control, plus one mute bit. It is a
5-bit volume range, where each step is nominally 1.5dB and
each output can be individually muted by either setting the
most significant bit (Mx5), and/or the mute bit (D15) to
″
1.
″
Mute
0
0
0
1
Default: 8000h
Mx5:Mx0
00 0000
01 1111
1X XXXX
XX XXXX
Function
0dB attenuation
46.5dB attenuation
46.5dB attenuation
mute
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
Mute
0
0
1
Default: 0000h
PV3:0
0000
1111
XXXX
Function
0dB attenuation
45dB attenuation
mute
Mixer Input Volume Registers (Index 0Ch - 18h)
These registers set the input volume levels including mute.
Each volume control is 5 bit which provides from a range of
+12dB gain to 34.5dB attenuation in 1.5dB steps. For stereo
ports, the left and right levels can be independently set. Mut-
ing a given port is accomplished by setting the MSB to 1.
Setting the MSB to 1 for stereo ports mutes both the left and
right channel. Register 0Eh has an additional 20dB boost for
a microphone level input. This is enabled by setting bit 6 of
register 0Eh to 1.
Mute
0
0
0
1
Default: 8008h (mono regs.), 8808h (stereo regs.)
Gx4:Gx0
00000
01000
11111
XXXXX
Function
+12dB gain
0dB gain
34.5dB attenuation
mute
Record Select Register (1Ah)
This register independently controls the source for the right
and left channel which will be recorded by the stereo ADC.
The default value is 0000h which corresponds to Mic in.
SL2:SL0
0
1
2
3
4
5
6
7
Left Record Source
Mic
CD In (L)
Video In (L)
Aux In (L)
Line In (L)
Stereo Mix (L)
Mono Mix (L)
Phone
SR2:SR0
0
1
2
3
4
5
6
7
Right Record Source
Mic
CD In (R)
Video In (R)
Aux In (R)
Line In (R)
Stereo Mix (R)
Mono Mix (R)
Phone
Record (Input) Gain Register (1Ch)
This registers controls the Record (Input) Gain level for the
stereo input selected via the Record Select Control Register
(1Ah). The gain can be programmed from 0dB to +22.5dB in
1.5dB steps. The level for the left and right channel can be
individually controlled. The input can also be muted by set-
ting the MSB to 1.
Mute
0
0
1
Default: 8000h
Gx3:Gx0
1111
0000
XXXX
Function
22.5dB gain
0dB gain
mute
General Purpose Register (20h)
This register controls many miscellaneous functions imple-
mented on the LM4549. The miscellaneous functions include
POP which allows the PCM to bypass the National 3D
Sound circuitry, 3D which enables or disables the National
3D Sound circuitry, MIX which selects the MONO_OUT
source, MS which selects the microphone mux source and
LPBK which connects the output of the stereo ADC to input
of the stereo DAC. LPBK provides for a digital loopthru path
when enabled.
BIT
Function
POP
PCM out path and mute, 0 = pre 3D, 1 =
post 3D
National 3D Sound on / off 1 = on
Mono output select 0 = Mix, 1 = Mic
Mic select 0 = Mic1 1 = Mic2
ADC/DAC loopback
3D
MIX
MS
LPBK
Powerdown Control / Status Register (26h)
This read/write register is used to monitor subsystem readi-
ness and also to program the LM4549 powerdown states.
The lower half of this register is read only with a
″
1
″
, indicat-
ing the subsection is ready. Writing to the lower 8 bits will
have no effect.
www.national.com
15
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM4549A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:AC ’97 Rev 2.1 Codec with Sample Rate Conversion and National 3D Sound |
| LM4549AVH | 制造商:Rochester Electronics LLC 功能描述:AC97 REV2.1 CODEC - Bulk 制造商:OC White Company 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP Tray |
| LM4549AVH WAF | 制造商:Texas Instruments 功能描述: |
| LM4549AVH/NOPB | 制造商:Texas Instruments 功能描述:Audio Codec 2ADC / 2DAC 18-Bit 48-Pin LQFP Tray |
| LM4549AVHX | 制造商:Rochester Electronics LLC 功能描述:AC97 REV2.1 CODEC - Bulk |
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