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參數(shù)資料
| 型號(hào)： | LM4050AI-4.1 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 自校準(zhǔn)12位帶符號(hào)串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器MUX和采樣/保持 |
| 文件頁數(shù)： | 36/41頁 |
| 文件大?。?/td> | 1152K |
| 代理商： | LM4050AI-4.1 |
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Application Hints
(Continued)
are shown in the table of Electrical Characteristics, and
spectral plots of S/(N + D) are included in the typical perfor-
mance curves.
The A/D converter’s noise and distortion levels will change
with the frequency of the input signal, with more distortion
and noise occurring at higher signal frequencies. This can be
seen in the S/(N + D) versus frequency curves.
Effective number of bits can also be useful in describing the
A/D’s noise performance. An ideal A/D converter will have
some amount of quantization noise, determined by its reso-
lution, which will yield an optimum S/N ratio given by the
following equation:
S/N = (6.02 x n + 1.76) dB
where n is the A/D’s resolution in bits.
S/(N + D) (or SINAD) is a combination of S/N (or SNR) and
distortion and is considered to be an overall measure of an
A/D converter performance. S/(N + D) is defined as:
and the effective number of Bits (ENOB) is defined as:
As an example, this device with a differential signed 5V,
1 kHz sine wave input signal will typically have a S/(N + D) of
77 dB, which is equivalent to 12.5 effective bits.
15.0 AN RS232 SERIAL INTERFACE
Shown on the following page is a schematic for an RS232
interface to any IBM and compatible PCs. The DTR, RTS,
and CTS RS232 signal lines are buffered via level transla-
tors and connected to the ADC12038’s DI, SCLK, and DO
pins, respectively. The D flip flop drives the CS control line.
01135444
Note:
V
A+
, V
D+
, and V
REF+
on the ADC12038 each have 0.01 μF and 0.1 μF chip caps, and 10 μF tantalum caps. All logic devices are bypassed with 0.1 μF
caps.
The assignment of the RS232 port is shown below
B7
X
X
B6
X
X
B5
X
X
B4
CTS
0
B3
X
X
B2
X
X
B1
X
RTS
B0
X
DTR
COM1 Input Address
Output Address
3FE
3FC
A sample program, written in Microsoft QuickBasic, is shown
on the next page. The program prompts for data mode select
instruction to be sent to the A/D. This can be found from the
Mode Programming table shown earlier. The data should be
entered in “1”s and “0”s as shown in the table with DI0 first.
Next the program prompts for the number of SCLKs required
for the programmed mode select instruction. For instance, to
send all “0”s to the A/D, selects CH0 as the +input, CH1 as
the input, 12-bit conversion, and 13-bit MSB first data
output format (if the sign bit was not turned off by a previous
instruction). This would require 13 SCLK periods since the
output data format is 13 bits. The part powers up with No
Auto Cal, No Auto Zero, 10 CCLK Acquisition Time, 12-bit
conversion, data out with sign, power up, 12- or 13-bit MSB
first, and user mode. Auto Cal, Auto Zero, Power Up and
A
www.national.com
36
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