參數(shù)資料
型號： LM4050AI-4.1
廠商： National Semiconductor Corporation
元件分類： 串行ADC
英文描述： Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold
中文描述： 自校準(zhǔn)12位帶符號串行I /辦公自動化/ D轉(zhuǎn)換器MUX和采樣/保持
文件頁數(shù)： 26/41頁
文件大?。?/td> 1152K
代理商： LM4050AI-4.1
TABLE 3. ADC12034 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with A/DIN1 tied to MUXOUT1
and A/DIN2 tied to MUXOUT2
CH0
CH1
CH2
+
A/D Input
Polarity
Assignment
Multiplexer
Output
Channel
Assignment
MUXOUT1
CH0
CH2
CH0
CH2
CH0
CH2
CH1
CH3
Mode
MUX
Address
DI0
L
L
L
L
H
H
H
H
DI1
L
L
H
H
L
L
H
H
DI2
L
H
L
H
L
H
L
H
CH3
COM
A/DIN1
+
+
+
+
+
+
A/DIN2
+
+
MUXOUT2
CH1
CH3
CH1
CH3
COM
COM
COM
COM
+
Differential
+
+
+
+
Single-Ended
+
+
TABLE 4. ADC12032 and ADC12030 Multiplexer Addressing
Analog Channel Addressed
and Assignment
with A/DIN1 tied to MUXOUT1
and A/DIN2 tied to MUXOUT2
CH0
CH1
+
+
A/D Input
Polarity
Assignment
Multiplexer
Output
Channel
Assignment
MUXOUT1
CH0
CH0
CH0
CH1
Mode
MUX
Address
DI0
L
L
H
H
DI1
L
H
L
H
COM
A/DIN1
+
+
+
A/DIN2
+
MUXOUT2
CH1
CH1
COM
COM
+
Differential
Single-Ended
+
Note:
ADC12030 and ADC12H030 do not have A/DIN1, A/DIN2, MUXOUT1
and MUXOUT2 pins.
TABLE 5. Mode Programming
ADC12038
ADC12034
ADC12030
and
ADC12032
DI0
DI0
DI1
DI1
DI2
DI2
DI3
DI4
DI3
DI5
DI4
DI6
DI5
DI7
DI6
Mode Selected
(Current)
DO Format
(next Conversion
Cycle)
DI0
DI1
DI2
DI3
DI4
DI5
See
Tables 2, 3
or
Table 4
See
Tables 2, 3
or
Table 4
See
Tables 2, 3
or
Table 4
L
L
See
Tables 2, 3
or
Table 4
See
Tables 2, 3
or
Table 4
See
Tables 2, 3
or
Table 4
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
L
H
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
H
L
L
L
12 Bit Conversion
12 Bit Conversion
8 Bit Conversion
12 Bit Conversion of Full-Scale
12 Bit Conversion
12 Bit Conversion
8 Bit Conversion
12 Bit Conversion of Offset
Auto Cal
Auto Zero
Power Up
Power Down
Read Status Register
Data Out without Sign
Data Out with Sign
Acquisition Time—6 CCLK Cycles
Acquisition Time—10 CCLK Cycles
Acquisition Time—18 CCLK Cycles
12 or 13 Bit MSB First
16 or 17 Bit MSB First
8 or 9 Bit MSB First
12 or 13 Bit MSB First
12 or 13 Bit LSB First
16 or 17 Bit LSB First
8 or 9 Bit LSB First
12 or 13 Bit LSB First
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
No Change
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A
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