
Application Information
(Continued)
output voltage was 1.8V, for example, then the value of R
needed to give the two supplies identical soft-start times
would be 205
.Atiming diagram for the equal soft-start time
case is shown in
Figure 2
.
TRACKING WITH EQUAL SLEW RATES
The tracking feature can alternatively be used not to make
both rails reach regulation at the same time but rather to
have similar rise rates (in terms of output dV/dt). In this case,
the tracking resistors can be determined based on the fol-
lowing equation:
For the example case of V
= 5V and V
= 1.8V, with
R
set to 1 k
as before, R
is calculated from the above
equation to be 887
. A timing diagram for the case of equal
slew rates is shown in
Figure 3
.
TRACKING AND SHUTDOWN SEQUENCING
LM3743 is designed to track the output of a master power
supply during start-up, but when the master supply powers
down the output capacitor of the LM3743 will discharge cycle
by cycle through the low-side FET. The off-time will reach
100% when the voltage at the track pin reaches zero volts.
This condition will persist as long as the master output
voltage is zero volts and the drivers of the LM3743 are still
on. For example if the load is required to not be discharged,
the drivers must be shut-off before the master powers down.
This is achieved by shutting down the LM3743 or bring V
below UVLO falling threshold. In this case the load will not be
discharged.
SHUTDOWN
The LM3743 IC can be put into shutdown mode by bringing
the voltage at the COMP/EN pin below 0.45V (typ). The
quiescent current during shutdown is approximately 6 μA
(typ). During shutdown both the high-side and low-side FETs
are disabled. The soft-start capacitor is discharged through
an internal FET so that the output voltage rises in a con-
trolled fashion when the part is enabled again. When en-
abled a 4 μA pull-up current increases the charge of the
compensation capacitors.
UNDER VOLTAGE LOCK-OUT (UVLO)
If V
CC
drops below 2.66V (typ), the chip enters UVLO mode.
UVLO consists of turning off the top and bottom FETs and
remaining in that condition until V
rises above 2.84V (typ).
As with shutdown, the soft-start capacitor is discharged
through an internal FET, ensuring that the next start-up will
be controlled by the soft-start circuitry.
MOSFET GATE DRIVE
The LM3743 has two gate drivers designed for driving
N-channel MOSFETs in synchronous mode. Power for the
high gate driver is supplied through the BOOT pin, while
driving power for the low gate is provided through the V
pin. The BOOT voltage is supplied from a local charge pump
structure which consists of a Schottky diode and 0.1 μF
capacitor, shown in
Figure 4
. Since the bootstrap capacitor
(C10) is connected to the SW node, the peak voltage im-
pressed on the BOOT pin is the sum of the input voltage
(V
) plus the voltage across the bootstrap capacitor (ignor-
ing any forward drop across the bootstrap diode). The boot-
strap capacitor is charged up by V
(called V
BOOT_DC
here)
whenever the upper MOSFET turns off.
20177431
FIGURE 2. Tracking with Equal Soft-Start Time
20177433
FIGURE 3. Tracking with Equal Slew Rate
20177434
FIGURE 4. Charge Pump Circuit and Driver Circuitry
L
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