
Circuit Description
OVERVIEW
The LM27966 is a white LED driver system based upon an
adaptive 1.5x/1x CMOS charge pump capable of supplying
up to 180mA of total output current. With two controlled
banks of constant current sinks (Main and AUX), the
LM27966 is an ideal solution for platforms requiring a single
white LED driver for main display and indicator lighting. The
tightly matched current sinks ensure uniform brightness from
the LEDs across the entire small-format display.
Each LED is configured in a common anode configuration,
with the peak drive current being programmed through the
use of an external R
resistor. An I
2
C compatible interface
is used to enable the device and vary the brightness within
the individual current sink banks. For Main Display LEDs, 32
levels of brightness control are available. The brightness
control is achieved through a mix of analog and pulse width
modulated (PWM) methods. D
AUX
has 4 analog brightness
levels available.
CIRCUIT COMPONENTS
Charge Pump
The input to the 1.5x/1x charge pump is connected to the V
IN
pin, and the regulated output of the charge pump is con-
nected to the V
pin. The recommended input voltage
range of the LM27966 is 3.0V to 5.5V. The device’s regu-
lated charge pump has both open loop and closed loop
modes of operation. When the device is in open loop, the
voltage at V
is equal to the gain times the voltage at the
input. When the device is in closed loop, the voltage at V
is regulated to 4.6V (typ.). The charge pump gain transitions
are actively selected to maintain regulation based on LED
forward voltage and load requirements. This allows the
charge pump to stay in the most efficient gain (1x) over as
much of the input voltage range as possible, reducing the
power consumed from the battery.
LED Forward Voltage Monitoring
The LM27966 has the ability to switch converter gains (1x or
1.5x) based on the forward voltage of the LED load. This
ability to switch gains maximizes efficiency for a given load.
Forward voltage monitoring occurs on all diode pins within
Main Display. At higher input voltages, the LM27966 will
operate in pass mode, allowing the P
OUT
voltage to track the
input voltage. As the input voltage drops, the voltage on the
D
X
pins will also drop (V
DX
= V
POUT
– V
LEDx
). Once any of
the active D
x
pins reaches a voltage approximately equal to
175mV, the charge pump will then switch to the gain of 1.5x.
This switchover ensures that the current through the LEDs
never becomes pinched off due to a lack of headroom on the
current sources.
Diode pin D5 can have the diode sensing circuity disabled
through the general purpose register if D5 is not going to be
used.
D
AUX
is not a monitored LED current sink.
RESET Pin
The LM27965 has a hardware reset pin (RESET) that allows
the device to be disabled by an external controller without
requiring an I
2
C write command. Under normal operation,
the RESET pin should be held high (logic ’1’) to prevent an
unwanted reset. When the RESET is driven low (logic ’0’), all
internal control registers reset to the default states and the
part becomes disabled. Please see the
Electrical Character-
istics
section of the datasheet for required voltage thresh-
olds.
I
2
C Compatible Interface
DATA VALIDITY
The data on SDIO line must be stable during the HIGH
period of the clock signal (SCL). In other words, state of the
data line can only be changed when CLK is LOW.
A pull-up resistor between VIO and SDIO must be greater
than [
(VIO-V
) / 3mA
] to meet the V
requirement on
SDIO. Using a larger pull-up resistor results in lower switch-
ing current with slower edges, while using a smaller pull-up
results in higher switching currents with faster edges.
START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I
2
C session. A START condition is defined as
SDIO signal transitioning from HIGH to LOW while SCL line
is HIGH. A STOP condition is defined as the SDIO transition-
ing from LOW to HIGH while SCL is HIGH. The I
2
C master
always generates START and STOP conditions. The I
2
C bus
is considered to be busy after a START condition and free
after a STOP condition. During data transmission, the I
2
C
master can generate repeated START conditions. First
START and repeated START conditions are equivalent,
function-wise. The data on SDIO line must be stable during
the HIGH period of the clock signal (SCL). In other words,
the state of the data line can only be changed when CLK is
LOW.
TRANSFERING DATA
Every byte put on the SDIO line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The master releases the SDIO line (HIGH) during the ac-
knowledge clock pulse. The LM27966 pulls down the SDIO
20190125
FIGURE 1. Data Validity Diagram
20190111
FIGURE 2. Start and Stop Conditions
L
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