參數(shù)資料
型號(hào): LM27402MHX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 1350 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 5 X 4.40 MM, 0.90 MM HEIGHT, 0.65 MM PITCH, ETSSOP-16
文件頁(yè)數(shù): 28/32頁(yè)
文件大?。?/td> 653K
代理商: LM27402MHX
Symbol
Parameter
Conditions
Min
Typ
Max
Units
OVER CURRENT
V
OFFSET
Comparator Voltage Offset
-5
0
5
mV
I
CS-
Current Limit Offset Current
V
CS- = 5V
9.5
10.0
10.5
A
GATE DRIVE
R
DSON1
High-Side FET Driver Pull-Up On
Resistance
V
CBOOT - VSW = 4.7V, IHG =
+100 mA
1.7
R
DSON2
High-Side FET Driver Pull-Down On
Resistance
V
CBOOT - VSW = 4.7V, IHG =
-100 mA
1.2
R
DSON3
Low-Side FET Driver Pull-Up On
Resistance
V
VDD = 4.7V, ILG = +100 mA
1.7
R
DSON4
Low-Side FET Driver Pull-Down On
Resistance
V
VDD = 4.7V, ILG = -100 mA
1.0
T
DT
Deadtime Timeout
F
SW = 500 kHz
40
ns
SOFT-START
I
SS
Soft-Start Source Current
V
SS/TRACK = 0V
2
3
4
A
R
SS_PD
Soft-Start Pull-Down Resistance
V
SS/TRACK = 0.6V
288
T
SS_INT
Internal Soft-Start Time
1.28
ms
POWERGOOD
I
PGS
PGOOD Low Sink Current
V
PGOOD = 0.2V, VFB = 0.75V
60
100
A
I
PGL
PGOOD Leakage Current
V
PGOOD = 5V
1
10
A
O
VT
Over-Voltage Threshold
V
FB Rising
114
117
120
%
O
VT_HYS
O
VT Hysteresis
V
FB Falling
2
%
U
VT
Under-Voltage Threshold
V
FB Rising
91
94
97
%
U
VT_HYS
U
VT Hysteresis
V
FB Falling
3
%
T
DEGLITCH
Deglitch Time
V
PGOOD Rising and Falling
20
s
ENABLE
V
EN
Enable Logic High Threshold
V
EN Rising
1.10
1.17
1.24
V
EN_HYS
Enable Hysteresis
V
EN Falling
100
mV
I
EN
Enable Pin Pull-Up Current
V
EN = 0V
2
A
FREQUENCY SYNCHRONIZATION
V
LH_SYNC
SYNC Pin Logic High
V
VDD = 4.7V
2.0
V
LL_SYNC
SYNC Pin Logic Low
V
VDD = 4.7V
0.8
V
SYNC
FSW_L
Minimum Clock Sync Frequency
200
kHz
SYNC
FSW_H
Maximum Clock Sync Frequency
1200
kHz
THERMAL SHUTDOWN
T
SHD
Thermal Shutdown
Temperature Rising
165
°C
T
SHD_HYS
Thermal Shutdown Hysteresis
Temperature Falling
15
°C
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor to each pin.
Note 3:
VDD is the output of an internal linear regulator. Under normal operating conditions where VIN is greater than 5.5V, VDD must not be connected to any
external voltage source. In an application where VIN is between 3.0V and 5.5V, it is recommended to connect VDD to VIN. In order to have better noise rejection
under these conditions, a 1
and 1F RC input filter may be used.
Note 4:
Tested on a four layer JEDEC board. Four vias are provided under the LLP exposed pad and nine vias are provided under the eTSSOP exposed pad.
5
www.national.com
LM27402
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